John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for operations. The supported operations are: RETIMER_FW_UPDATE_PORT_INFO 0 RETIMER_FW_UPDATE_PD_SUSPEND 1 RETIMER_FW_UPDATE_PD_RESUME 2 RETIMER_FW_UPDATE_GET_MUX 3 RETIMER_FW_UPDATE_SET_USB 4 RETIMER_FW_UPDATE_SET_SAFE 5 RETIMER_FW_UPDATE_SET_TBT 6 RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867 TEST=Booted to kerenl and verified RFWU entry from ACPI DSDT ERAM.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49051/1
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b..7b1a663 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -81,6 +81,7 @@ Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power + RFWU, 8, // Retimer Firmware Update }
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG@21 PS1, Line 21: kerenl kernel (which version)
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG@21 PS1, Line 21: verified RFWU entry from ACPI DSDT ERAM How can this be verified?
John Zhao has uploaded a new patch set (#2) to the change originally created by John Zhao. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for operations. The supported operations are: RETIMER_FW_UPDATE_PORT_INFO 0 RETIMER_FW_UPDATE_PD_SUSPEND 1 RETIMER_FW_UPDATE_PD_RESUME 2 RETIMER_FW_UPDATE_GET_MUX 3 RETIMER_FW_UPDATE_SET_USB 4 RETIMER_FW_UPDATE_SET_SAFE 5 RETIMER_FW_UPDATE_SET_TBT 6 RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867 TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49051/2
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG@21 PS1, Line 21: verified RFWU entry from ACPI DSDT ERAM
How can this be verified?
Just acpidump, acpixtract, iasl and then review the dsdt.dsl EC's ERAM field, where RFWU is defined at offset 0x14.
https://review.coreboot.org/c/coreboot/+/49051/1//COMMIT_MSG@21 PS1, Line 21: kerenl
kernel (which version)
any version kernel.
Attention is currently required from: John Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2: Mind rebasing these 3 patches so the order is (bottom to top):
48630 (enable retimer fw upgrade mux interaction) 49051 (this one) 49257 (Provide EC access for Retimer firmware update)
Attention is currently required from: Tim Wawrzynczak, John Zhao. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
Mind rebasing these 3 patches so the order is (bottom to top): […]
done
Attention is currently required from: John Zhao, Rajmohan Mani. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for operations. The supported operations are: RETIMER_FW_UPDATE_PORT_INFO 0 RETIMER_FW_UPDATE_PD_SUSPEND 1 RETIMER_FW_UPDATE_PD_RESUME 2 RETIMER_FW_UPDATE_GET_MUX 3 RETIMER_FW_UPDATE_SET_USB 4 RETIMER_FW_UPDATE_SET_SAFE 5 RETIMER_FW_UPDATE_SET_TBT 6 RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867 TEST=Booted to kernel and verified RFWU entry from ACPI DSDT ERAM field.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49051 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b..7b1a663 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -81,6 +81,7 @@ Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power + RFWU, 8, // Retimer Firmware Update }
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)