John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49051 )
Change subject: ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update ......................................................................
ec/google/chromeec: Add RFWU into EC RAM for Retimer firmware update
The RFWU byte is defined as Bits[3:0] for port number and Bits[7:4] for operations. The supported operations are: RETIMER_FW_UPDATE_PORT_INFO 0 RETIMER_FW_UPDATE_PD_SUSPEND 1 RETIMER_FW_UPDATE_PD_RESUME 2 RETIMER_FW_UPDATE_GET_MUX 3 RETIMER_FW_UPDATE_SET_USB 4 RETIMER_FW_UPDATE_SET_SAFE 5 RETIMER_FW_UPDATE_SET_TBT 6 RETIMER_FW_UPDATE_DISCONNECT 7
BUG=b:162528867 TEST=Booted to kerenl and verified RFWU entry from ACPI DSDT ERAM.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I1ba04c6357b6fd0cc33ffce33e7e430539bace79 --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/49051/1
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 218d08b..7b1a663 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -81,6 +81,7 @@ Offset (0x12), BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power + RFWU, 8, // Retimer Firmware Update }
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)