Change in coreboot[master]: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
This patch ensures that bootblock/pch.c clear PCI_COMMAND_MASTER (BIT 2) prior to program PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1).
Also performs beiow operations 1. Use pci_and_config16 instead pci_read and write 2. Use setbits32 instread mmio read and write
Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44205/1
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index ae52f45..5dd9fb6 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -59,26 +59,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 6ebf910..0503455 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -40,26 +40,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 1260bc8..12b210d 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -44,26 +44,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9fc5ce1..e8cfc52 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -49,26 +49,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((char *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 1: Code-Review+2
(6 comments)
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@9 PS1, Line 9: This patch ensures that bootblock/pch.c In `bootblock/pch.c`, clear PCI_COMMAND_MASTER ...
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@10 PS1, Line 10: prior to program `prior to programming` or `before programming`
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@13 PS1, Line 13: beiow be*l*ow
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@13 PS1, Line 13: performs perform
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@14 PS1, Line 14: _ replace `_` with a space
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@15 PS1, Line 15: instread instead of
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44205
to look at the new patch set (#2).
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1).
Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write
Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44205/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 1:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@9 PS1, Line 9: This patch ensures that bootblock/pch.c
In `bootblock/pch.c`, clear PCI_COMMAND_MASTER ...
Ack
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@10 PS1, Line 10: prior to program
`prior to programming` or `before programming`
Ack
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@13 PS1, Line 13: performs
perform
Ack
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@13 PS1, Line 13: beiow
be*l*ow
Ack
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@14 PS1, Line 14: _
replace `_` with a space
Ack
https://review.coreboot.org/c/coreboot/+/44205/1//COMMIT_MSG@15 PS1, Line 15: instread
instead of
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG@11 PS2, Line 11: along with PCI_COMMAND_MEMORY (BIT 1). Is that required by some specification?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/cannonlake/bo... PS2, Line 75: (char *) void *?
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/tigerlake/boo... PS2, Line 50: soc_config_pwrmbase Looks like this is a good candidate to move to common/block/pmc?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44205/2//COMMIT_MSG@11 PS2, Line 11: along with PCI_COMMAND_MEMORY (BIT 1).
Is that required by some specification?
in general PCI resource enabling program says to disable bus master cycle before assigning a new BAR to avoid cycle is getting decoded if already BAR been implemented. Hence its safe to make MMIO and BUS master disable prior to BAR assignment and enable it back after the programming done
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/cannonlake/bo... File src/soc/intel/cannonlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/cannonlake/bo... PS2, Line 75: (char *)
void *?
Ack
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/pch.c:
https://review.coreboot.org/c/coreboot/+/44205/2/src/soc/intel/tigerlake/boo... PS2, Line 50: soc_config_pwrmbase
Looks like this is a good candidate to move to common/block/pmc?
yes, we might need to handle using PMC_V1 and V2 as soc_config_pwrmbase programming logic is different between SKL-KBL/APL-GLK/CNL-ICL-TGL-ADL
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44205
to look at the new patch set (#3).
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1).
Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write
Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 16 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44205/3
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 3: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
Patch Set 3: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44205 )
Change subject: soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE ......................................................................
soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1).
Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write
Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 4 files changed, 16 insertions(+), 40 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index ae52f45..e1f0548 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -59,26 +59,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 6ebf910..f36bd31 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -40,26 +40,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 1260bc8..f59d9c9 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -44,26 +44,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 9fc5ce1..63beeaa 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -49,26 +49,20 @@
static void soc_config_pwrmbase(void) { - uint32_t reg32; - uint16_t reg16; - /* * Assign Resources to PWRMBASE - * Clear BIT 1-2 Command Register + * Clear BIT 1-2 Command Register */ - reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MEMORY); - pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16); + pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Program PWRM Base */ pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
/* Enable Bus Master and MMIO Space */ - pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
/* Enable PWRM in PMC */ - reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL)); - write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN); + setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); }
void bootblock_pch_early_init(void)
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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Paul Menzel (Code Review)
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Subrata Banik (Code Review)
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Tim Wawrzynczak (Code Review)