soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE

In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to
programming PWRMBASE and enable BIT 2 after programming PWRMBASE
along with PCI_COMMAND_MEMORY (BIT 1).

Also perform below operations
1. Use pci_and_config16 instead of pci read and write
2. Use setbits32 instead of mmio read and write

Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/icelake/bootblock/pch.c
M src/soc/intel/jasperlake/bootblock/pch.c
M src/soc/intel/tigerlake/bootblock/pch.c
4 files changed, 16 insertions(+), 40 deletions(-)