Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPTC ......................................................................
sb/intel/ibexpeak: Fix enabling HPTC
RCBA_HPTC needs to be read back to properly work. This fixes SeaBIOS endlessly waiting for input instead of booting the default entry.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35757/1
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 4a25181..8088827 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -393,6 +393,7 @@ reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + RCBA32(HPTC); /* Read back for it to work */
write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); }
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPTC ......................................................................
Patch Set 2:
(2 comments)
Is the problem also visible in the OS? Should SeaBIOS (or payloads in general) also be fixed somehow to work around firmware bugs?
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG@9 PS2, Line 9: RCBA_HPTC needs to be read back to properly work. : This fixes SeaBIOS endlessly waiting for input instead of booting the : default entry. Please do not break the line, just because the sentence ends there. If it’s a paragraph, please add a blank line between them.
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/lpc.c:
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... PS2, Line 397: RCBA32(HPTC); /* Read back for it to work */ Mention SeaBIOS as an exapmle?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPTC ......................................................................
Patch Set 2:
(2 comments)
Patch Set 2:
(2 comments)
Is the problem also visible in the OS? Should SeaBIOS (or payloads in general) also be fixed somehow to work around firmware bugs?
Linux works around/fixes this in arch/x86/kernel/quirks.c (see ich_force_enable_hpet). SeaBIOS might be fixed but as payloads should be as platform independent as possible, it makes sense to fix in the hardware init, coreboot in this case.
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG@9 PS2, Line 9: RCBA_HPTC needs to be read back to properly work. : This fixes SeaBIOS endlessly waiting for input instead of booting the : default entry.
Please do not break the line, just because the sentence ends there. […]
Ack
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/lpc.c:
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... PS2, Line 397: RCBA32(HPTC); /* Read back for it to work */
Mention SeaBIOS as an exapmle?
It applies to everything that uses HPET.
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35757
to look at the new patch set (#3).
Change subject: sb/intel/ibexpeak: Fix enabling HPTC ......................................................................
sb/intel/ibexpeak: Fix enabling HPTC
RCBA_HPTC needs to be read back to properly work.
This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35757/3
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35757
to look at the new patch set (#4).
Change subject: sb/intel/ibexpeak: Fix enabling HPTC ......................................................................
sb/intel/ibexpeak: Fix enabling HPTC
RCBA_HPTC needs to be read back to properly work.
This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35757/4
Hello Kyösti Mälkki, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35757
to look at the new patch set (#5).
Change subject: sb/intel/ibexpeak: Fix enabling HPET ......................................................................
sb/intel/ibexpeak: Fix enabling HPET
RCBA_HPTC needs to be read back to properly work.
This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35757/5
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPET ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35757/2//COMMIT_MSG@9 PS2, Line 9: RCBA_HPTC needs to be read back to properly work. : This fixes SeaBIOS endlessly waiting for input instead of booting the : default entry.
Ack
Done
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... File src/southbridge/intel/ibexpeak/lpc.c:
https://review.coreboot.org/c/coreboot/+/35757/2/src/southbridge/intel/ibexp... PS2, Line 397: RCBA32(HPTC); /* Read back for it to work */
It applies to everything that uses HPET.
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPET ......................................................................
Patch Set 7: Code-Review+2
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35757 )
Change subject: sb/intel/ibexpeak: Fix enabling HPET ......................................................................
sb/intel/ibexpeak: Fix enabling HPET
RCBA_HPTC needs to be read back to properly work.
This fixes SeaBIOS endlessly waiting for input instead of booting the default entry. Linux already fixes this itself.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35757 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/southbridge/intel/ibexpeak/lpc.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index ec9b045..e433530 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -394,6 +394,7 @@ reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + RCBA32(HPTC); /* Read back for it to work */
write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); }
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Paul Menzel (Code Review)