Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
asus/a88xm-e: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 207 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/1
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c index 2e08188..5caf224 100644 --- a/src/mainboard/asus/a88xm-e/mainboard.c +++ b/src/mainboard/asus/a88xm-e/mainboard.c @@ -6,26 +6,54 @@ #include <device/device.h> #include <southbridge/amd/common/amd_pci_util.h>
-static const u8 mainboard_picr_data[] = { - 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, -}; -static const u8 mainboard_intr_data[84] = { - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, - 0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13, +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> + +extern const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]; +extern const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ picr_data[PIRQ_A] if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D} }, */ + {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ };
/* PIRQ Setup */ static void pirq_setup(void) { + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } @@ -36,6 +64,7 @@ msr_t msr;
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ pirq_setup();
msr = rdmsr(LS_CFG_MSR); diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c index b9e743c..5d9731f 100644 --- a/src/mainboard/asus/a88xm-e/mptable.c +++ b/src/mainboard/asus/a88xm-e/mptable.c @@ -1,10 +1,61 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/io.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <stdint.h> #include <string.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> + +/* + * Based on 51205_Bolton_FCH_BIOS_Dev_Guide.pdf. Acronyms: + * + * SCI - System Controller Interrupt, + * SMBUS - System Management Bus, + * ASF - Advanced Synchronization Facility, + * HDA - HD Audio, + * SD - SD Flash Controller, + * GEC - Gigabit Ethernet Controller, + * PerMon - Performance Monitor, + * IMC - Integrated Memory Controller, + * GPP - PCIe General Purpose Ports. + */ + +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0xAA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x05, 0x04, 0x05, + /* IDE, SATA */ + [0x40] = 0x1F, 0x07, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x1F, 0x1F, + /* Misc-nil,0,1,2, INTA-INTD from Serial irq */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + /* SCI, SMBUS0, ASF, HDA, SD, GEC, PerMon */ + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, + /* IMC INT0-INT5 */ + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + /* USB Devs: 18 INTA#,B#; 19 INTA#,B#; 22 INTA#,B#; 20 INTC# */ + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, + /* IDE, SATA */ + [0x40] = 0x1F, 0x13, + /* GPP Int0-Int3 */ + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F +};
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { @@ -37,92 +88,150 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+ /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8);
+ /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA ");
- /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
- /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\ - bus_isa, (intr), (apicid), (pin)) + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
/* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\ - (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
- /* IOMMU */ - PCI_INT(0x0, 0x0, 0x0, 0x10); - PCI_INT(0x0, 0x0, 0x1, 0x11); - PCI_INT(0x0, 0x0, 0x2, 0x12); - PCI_INT(0x0, 0x0, 0x3, 0x13); + /* IOMMU: 0:00.02 - IRQ 3 */ + PCI_INT(0x0, 0x00, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x00, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x00, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x00, 0x3, intr_data_ptr[PIRQ_D]);
- /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_A]); + /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_B]);
- /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); + /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ + PCI_INT(0x0, 0x02, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x02, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x02, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x02, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ + PCI_INT(0x0, 0x04, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x0, 0x04, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x04, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x04, 0x3, intr_data_ptr[PIRQ_D]); + /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ + PCI_INT(0x0, 0x05, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x05, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x05, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x05, 0x3, intr_data_ptr[PIRQ_A]); + /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ + PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x0, 0x06, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x06, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x0, 0x06, 0x3, intr_data_ptr[PIRQ_A]);
- /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); - - /* on board NIC & Slot PCIE. */ + /* USB XHCI: 0:10.00 - IRQ 5 */ + PCI_INT(0x0, 0x10, 0x0, intr_data_ptr[PIRQ_C]); + /* SATA: 0:11.00 - IRQ 7 */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + /* USB OHCI1: 0:12.00 - IRQ 5 */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + /* USB EHCI1: 0:12.02 - IRQ 4 */ + PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]); + /* USB OHCI2: 0:13.00 - IRQ 5 */ + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + /* USB EHCI2: 0:13.02 - IRQ 4 */ + PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]); + /* USB OHCI3: 0:16.00 - IRQ 5 */ + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + /* USB EHCI3: 0:16.02 - IRQ 4 */ + PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]); + /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + /* USB OHCI4: 0:14.05 - IRQ 5 */ + PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_C]);
/* PCI slots */ struct device *dev = pcidev_on_root(0x14, 4); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); + /* PCI slot 0 */ + PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); }
- /* PCIe Lan */ - PCI_INT(0x0, 0x06, 0x0, 0x13); + /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ + PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_B]); + /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ + PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_C]); + /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ + PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_D]); + /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ + PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_A]);
- /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); + /* Discrete Graphics (dGPU) 1:00.00 behind a 0:02.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x1, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x1, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x1, 0x0, 0x3, intr_data_ptr[PIRQ_D]);
- /* Local Ints: Type IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* 2:00.00 behind a 0:04.00 PCIe GPP - IRQ 3 */ + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_A]); + PCI_INT(0x2, 0x0, 0x1, intr_data_ptr[PIRQ_B]); + PCI_INT(0x2, 0x0, 0x2, intr_data_ptr[PIRQ_C]); + PCI_INT(0x2, 0x0, 0x3, intr_data_ptr[PIRQ_D]); + + /* 3:00.00 behind a 0:05.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x3, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x3, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x3, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /* Onboard Ethernet (Eth) 4:00.00 behind a 0:06.00 PCIe GPP - IRQ 4 */ + PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_B]); + PCI_INT(0x4, 0x0, 0x1, intr_data_ptr[PIRQ_C]); + PCI_INT(0x4, 0x0, 0x2, intr_data_ptr[PIRQ_D]); + PCI_INT(0x4, 0x0, 0x3, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */
/* Compute the checksums */
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 1:
This is similar to CB:48161 for Lenovo G505S. Yes, imperfect, but still much better than what's in a tree - confirmed by KolibriOS ;-)
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 1:
(24 comments)
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... File src/mainboard/asus/a88xm-e/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 28: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 29: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 30: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 31: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 32: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 33: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 34: {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 35: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 36: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 37: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 38: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 39: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 40: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 41: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 42: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 43: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 44: {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 45: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 46: {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 47: {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 48: {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 49: {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 132: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/1/src/mainboard/asus/a88xm-e/... PS1, Line 231: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Attention is currently required from: Mike Banon. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48424/comment/160a5b15_c3eb721f PS1, Line 13: How did you determine the values? Just copying them from the Asus AM1I-A?
https://review.coreboot.org/c/coreboot/+/48424/comment/0d26ec08_33b10045 PS1, Line 15: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; Can you please paste one of these messages in the git commit message?
Patchset:
PS1: Very nice.
File src/mainboard/asus/a88xm-e/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48424/comment/e6ddcc2a_550d8301 PS1, Line 17: * This table defines the index into the picr/intr_data Please rewrap the comment to use 72 characters per line.
Attention is currently required from: Mike Banon. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1: Please see the two change-sets below for a solution for all AGESA boards.
1. https://review.coreboot.org/c/coreboot/+/38564 2. https://review.coreboot.org/c/coreboot/+/38313
Attention is currently required from: Paul Menzel. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48424/comment/7d3c978c_f3409956 PS1, Line 13:
How did you determine the values? Just copying them from the Asus AM1I-A?
No, there is a certain unwritten algorithm which helped to get the board-specific values for A88XM-E (and G505S). I have trouble remembering it, but it could be understood by looking at am1i-a and other boards as the examples - and in any case I'm not sure I did it 100% correctly, since all this stuff is really tricky, but I tried my best.
https://review.coreboot.org/c/coreboot/+/48424/comment/353e85c2_fe701195 PS1, Line 15: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg;
Can you please paste one of these messages in the git commit message?
One of the possible messages is "irq 17: nobody cared (try booting with the "irqpoll" option)". There were also the more prominent ones, which caused the kernel oopses/panicks but I have trouble locating them at the moment. The thing is, if you've done the IRQ routing really wrong, it's likely the kernel will let you know (or you'd just notice that some device isn't working).
Patchset:
PS1:
Please see the two change-sets below for a solution for all AGESA boards. […]
I've already tried going this route but lacked something - time, patience or skill (you decide) - to figure out the IRQ tables autogeneration. So I did it what I could: fixed the IRQs for the three boards which I own, statically and with a lot of trial and error. If someone else also wants to fix the IRQs of his board the same way, he could use my am1i-a/a88xm-e/g505s IRQ patches as the examples. https://review.coreboot.org/c/coreboot/+/48427 - "AMD good IRQs"
File src/mainboard/asus/a88xm-e/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48424/comment/74ed88f8_a184c2dd PS1, Line 17: * This table defines the index into the picr/intr_data
Please rewrap the comment to use 72 characters per line.
This should be done in the follow-up change - and not just for ASUS A88XM-E but for the many boards across the tree. Any optional changes like this comment change, if done alone - would make it harder to compare in kdiff3/meld vs the other boards, so shouldn't be done unless truly necessary.
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48424
to look at the new patch set (#2).
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
asus/a88xm-e: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 206 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/2
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 2:
(24 comments)
File src/mainboard/asus/a88xm-e/mainboard.c:
https://review.coreboot.org/c/coreboot/+/48424/comment/58584099_e57605a5 PS2, Line 28: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/b6ca535f_b738739a PS2, Line 29: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/0246f7de_7054b525 PS2, Line 30: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/46f8da79_d0d4ef6e PS2, Line 31: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/a10e6128_149d4e75 PS2, Line 32: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/efb180d7_6bb03a45 PS2, Line 33: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/c040275f_db11279d PS2, Line 34: {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/a39210d9_4df16f43 PS2, Line 35: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/51d0ff91_a95be8f9 PS2, Line 36: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/f7706a45_3be04301 PS2, Line 37: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/c675b006_20576622 PS2, Line 38: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/e26d1aaf_ca0a5d91 PS2, Line 39: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/ad3d69db_fe6da6d7 PS2, Line 40: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/f9fa8922_61542a79 PS2, Line 41: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/e2ab66d7_e6954e6d PS2, Line 42: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/d79b6569_4dd61360 PS2, Line 43: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/e8258db9_95a12ba6 PS2, Line 44: {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/b65a90e8_d481edaf PS2, Line 45: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/c3d8e88b_657a2e05 PS2, Line 46: {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/47f5e02c_5dc3a470 PS2, Line 47: {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/e073535b_0d917efd PS2, Line 48: {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/a51d4eba_6fe84080 PS2, Line 49: {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ line over 96 characters
File src/mainboard/asus/a88xm-e/mptable.c:
https://review.coreboot.org/c/coreboot/+/48424/comment/a1de0142_48da9754 PS2, Line 132: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
https://review.coreboot.org/c/coreboot/+/48424/comment/8bfc1868_abd6b1f4 PS2, Line 231: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 3:
(24 comments)
File src/mainboard/asus/a88xm-e/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/332ab834_28cb7529 PS3, Line 28: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/3a648da2_92edbac1 PS3, Line 29: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/37002721_819022e2 PS3, Line 30: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/ef1f0906_d3b034f2 PS3, Line 31: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/96252e82_1819a925 PS3, Line 32: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/8fe887f8_e55494ff PS3, Line 33: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/f0bea5cc_ba991a84 PS3, Line 34: {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/601405d5_eaa0c161 PS3, Line 35: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/61bd3d23_733905e1 PS3, Line 36: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/edebe153_05158577 PS3, Line 37: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/7cd405f0_527e9d0e PS3, Line 38: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/c6d373ef_bb57788f PS3, Line 39: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/2ec74265_e3d27197 PS3, Line 40: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/3cd54dcd_28c5acf6 PS3, Line 41: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/3febf40e_d9877a94 PS3, Line 42: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/e8ef7c61_53281c9d PS3, Line 43: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/b8b701b6_a1d03dbc PS3, Line 44: {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/950d7c6c_7f5e919d PS3, Line 45: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/9b069bb3_3ecfaa5c PS3, Line 46: {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/4eb23816_06973873 PS3, Line 47: {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/d8b1b7d8_85dd3f49 PS3, Line 48: {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/6971b585_94601fd7 PS3, Line 49: {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ line over 96 characters
File src/mainboard/asus/a88xm-e/mptable.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/9ab202ec_0028824f PS3, Line 132: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117709): https://review.coreboot.org/c/coreboot/+/48424/comment/7d066404_583154c2 PS3, Line 231: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48424
to look at the new patch set (#4).
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
asus/a88xm-e: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 203 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/4
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 4:
(24 comments)
File src/mainboard/asus/a88xm-e/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/9c304065_ca20359a PS4, Line 28: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/01098f7b_d488ea99 PS4, Line 29: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/ebd4c7a9_1515558d PS4, Line 30: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/edbecbe7_13874b75 PS4, Line 31: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/958e1f47_d1e7ac42 PS4, Line 32: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/4506b7c3_a91d359e PS4, Line 33: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/41d180b5_1c0f5341 PS4, Line 34: {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/2b33db1e_32dba284 PS4, Line 35: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/dd17cb23_6be88549 PS4, Line 36: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/714068b4_33336564 PS4, Line 37: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/385990de_e659ab1c PS4, Line 38: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/dd4450bf_cf7ae5db PS4, Line 39: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/5ac63466_51c4a7dd PS4, Line 40: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/fcdad215_d1781a17 PS4, Line 41: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/a63443c5_00bb78f6 PS4, Line 42: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/4c7c2c76_d08b3d89 PS4, Line 43: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/1ab6e49b_2e1cfe2a PS4, Line 44: {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/b6b9d406_b4f2fa11 PS4, Line 45: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/a91382e7_91fcc4c8 PS4, Line 46: {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/44b517dd_a762a031 PS4, Line 47: {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/f8db01d4_6282dd2a PS4, Line 48: {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/bed522ce_34350525 PS4, Line 49: {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ line over 96 characters
File src/mainboard/asus/a88xm-e/mptable.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/778b3d41_3ad23e0f PS4, Line 126: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-127242): https://review.coreboot.org/c/coreboot/+/48424/comment/8afe14ca_6b85e52e PS4, Line 225: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Attention is currently required from: Paul Menzel. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 5:
(24 comments)
File src/mainboard/asus/a88xm-e/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/12fb9d7e_a3336d70 PS5, Line 28: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/37258c15_bc3f0525 PS5, Line 29: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/cdfaf4c6_c9c16b10 PS5, Line 30: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/70c04b25_28740bdc PS5, Line 31: {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to dGPU 1:00.00: 0:02.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/e07cef42_44748d65 PS5, Line 32: {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe GPP to 2:00.00: 0:04.00 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/7a61aa1a_f0abe9fa PS5, Line 33: {NB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to 3:00.00: 0:05.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/f68bcbf3_9a8d4d14 PS5, Line 34: {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* PCIe GPP to Eth 4:00.00: 0:06.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/ac3b9a94_76417e9b PS5, Line 35: {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB XHCI: 0:10.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/8c1bec55_462b38ce PS5, Line 36: {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA: 0:11.00 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/99377b92_6f8833b5 PS5, Line 37: {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI1: 0:12.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/7263c4ce_aec86ef3 PS5, Line 38: {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC} }, /* USB EHCI1: 0:12.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/ca62c8f1_60180a9f PS5, Line 39: {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI2: 0:13.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/542614c8_593814c0 PS5, Line 40: {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC} }, /* USB EHCI2: 0:13.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/7e4f4838_9c6dd98d PS5, Line 41: {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* USB OHCI3: 0:16.00 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/38894ab7_0ef8c1df PS5, Line 42: {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC} }, /* USB EHCI3: 0:16.02 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/153129bb_6ecfa299 PS5, Line 43: {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* Southbridge HD Audio: 0:14.02 - IRQ 3 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/35cab0d4_b89a4db1 PS5, Line 44: {SB_PCI_PORT_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_NC, PIRQ_NC} }, /* Southbridge PCI Port: 0:14.04 - IRQ 11 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/cac1b506_0e54e252 PS5, Line 45: {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC} }, /* USB OHCI4: 0:14.05 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/ed8dd58b_78dc764b PS5, Line 46: {SB_PCIE_PORT1_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A} }, /* Southbridge PCIe Port 1: 0:15.00 - IRQ 4 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/145c96b3_de5c975f PS5, Line 47: {SB_PCIE_PORT2_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B} }, /* Southbridge PCIe Port 2: 0:15.01 - IRQ 5 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/b45d40dd_c7d90156 PS5, Line 48: {SB_PCIE_PORT3_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C} }, /* Southbridge PCIe Port 3: 0:15.02 - IRQ 7 */ line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/82ea8eef_0d544ab1 PS5, Line 49: {SB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} } /* Southbridge PCIe Port 4: 0:15.03 - IRQ 3 */ line over 96 characters
File src/mainboard/asus/a88xm-e/mptable.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/a2920b64_958f9f2d PS5, Line 126: smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-131799): https://review.coreboot.org/c/coreboot/+/48424/comment/5b78795c_c0d787b0 PS5, Line 225: smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)) line over 96 characters
Attention is currently required from: Paul Menzel. Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48424
to look at the new patch set (#7).
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
asus/a88xm-e: properly program the IRQ tables
IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for ASUS A88XM-E: all the fam15h boards have these "bad IRQs". OS like Linux still finds a way, but Kolibri can't see the IRQ table.
With this change applied: * A88XM-E boots fine to Linux - no angry IRQ-related messages at dmesg; * KolibriOS sees 16 IRQs in a table and could successfully attach a driver to Realtek RTL8168 onboard Ethernet controller with an IRQ 7.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9a6ab9e24a828ebaffe87205a2ce0ebd811a935d --- M src/mainboard/asus/a88xm-e/mainboard.c M src/mainboard/asus/a88xm-e/mptable.c 2 files changed, 203 insertions(+), 68 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48424/7
Attention is currently required from: Paul Menzel.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48424 )
Change subject: asus/a88xm-e: properly program the IRQ tables ......................................................................
Patch Set 8: Verified+1
(3 comments)
File src/mainboard/asus/a88xm-e/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164825): https://review.coreboot.org/c/coreboot/+/48424/comment/a487b2a0_7ff05a97 PS8, Line 27: {IOMMU_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* IOMMU: 0:00.02 - IRQ 3 */ line length of 122 exceeds 119 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164825): https://review.coreboot.org/c/coreboot/+/48424/comment/7c9cee7d_db50bdc2 PS8, Line 28: {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* APU Integrated Graphics: 0:01.00 - IRQ 3 */ line length of 122 exceeds 120 columns
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-164825): https://review.coreboot.org/c/coreboot/+/48424/comment/a7252d3f_021d2af5 PS8, Line 29: {ACTL_DEVFN, {PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC} }, /* APU HDMI Audio Controller: 0:01.01 - IRQ 4 */ line length of 122 exceeds 121 columns
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build bot (Jenkins) (Code Review) -
Mike Banon (Code Review)
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Paul Menzel (Code Review)