Change in coreboot[master]: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Inte...
Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP
This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree.
This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialisation, which was not sufficient during FSP initialisation which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..aa009bb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -593,6 +593,19 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = {
+ #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + + /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + + /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + + /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + #endif
};
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9648ac3..40da8eb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1"
+ # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 126cab0..6ee52a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1"
+ # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "0" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 429d5da..e824ac9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1"
+ # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "0" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C/D/F
Lean Sheng Tan has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP
This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree.
This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialization, which was not sufficient during FSP initialization which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/2
Hello Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34159
to look at the new patch set (#3).
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP
This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree.
This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialization, which was not sufficient during FSP-S which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/3
Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 3:
Look good to me but need Subrata agree on the WHL changes.
Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 3: Code-Review+1
Hello Subrata Banik, Aamir Bohra, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34159
to look at the new patch set (#4).
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP
This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree.
This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialization, which was not sufficient during FSP-S which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 51 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/4
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
Sounds like a bug to me. If so please document it that future FSP users won't have the same problem.
Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 596: SOC_INTEL_CANNONLAKE_PCH_H Issue only happened on CNL-H but not CNL-LP? But the changes in devicetree.cb seems generic?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 596: #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) remove tab
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... File src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 18: register "DdiPortFHpd" = "0" if display is coming using coreboot + depthcharge on WHL-U which i know without this CL, then why we are changing this code ?
then it would be something specific on panel ?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
(7 comments)
Please split the commit into two, as the two changes seem to be fixing separate issues.
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@6 PS4, Line 6: : mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL : Intel RVP The summary has to fit on one line.
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@11 PS4, Line 11: not showing up in UEFI shell So nothing is displayed or UEFI shell has a command to list the found displays?
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@11 PS4, Line 11: are is
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@12 PS4, Line 12: DDi DDI?
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@14 PS4, Line 14: UEFI : Payload Which one? TianoCore?
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@15 PS4, Line 15: Payload payload
https://review.coreboot.org/c/coreboot/+/34159/4//COMMIT_MSG@18 PS4, Line 18: This issue is fixed by programming eDP GPIO's in bootblock stage and Please add a blank line above, or do not break the line.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
(2 comments)
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... File src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 596: SOC_INTEL_CANNONLAKE_PCH_H
Issue only happened on CNL-H but not CNL-LP? But the changes in devicetree. […]
No it is not generic, CNL-H and CNL-LP have some different sets of GPIO configs
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 596: #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
remove tab
Done
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
Patch Set 4:
(7 comments)
Please split the commit into two, as the two changes seem to be fixing separate issues.
will do.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
Patch Set 4:
Sounds like a bug to me. If so please document it that future FSP users won't have the same problem.
Noted, will get back to you on this in a day.
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... File src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/34159/4/src/mainboard/intel/coffeel... PS4, Line 18: register "DdiPortFHpd" = "0"
if display is coming using coreboot + depthcharge on WHL-U which i know without this CL, then why we […]
The previous configuration was not working on us for RVP. I will let Will comment on this, but from my understanding their focus is on Google platform. We fixed this as we started to enable eDP only recently.
Hello Subrata Banik, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Boon Tiong Teo, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34159
to look at the new patch set (#5).
Change subject: mb/intel/coffeelake_rvp: Enabling eDP on CFL-H, CFL-S, WHL Intel RVP ......................................................................
mb/intel/coffeelake_rvp: Enabling eDP on CFL-H, CFL-S, WHL Intel RVP
This patch set the right eDP DDi (Digital Display Interface) port configuration on both CFL-H & S, and WHL Intel RVP platform to enable eDP display on CFL-H, CFL-S, WHL Intel RVP.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 51 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/5
Lean Sheng Tan has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/34159 )
Change subject: mb/intel/coffeelake_rvp: Enabling eDP on CFL-H, CFL-S, WHL Intel RVP ......................................................................
Abandoned
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Boon Tiong Teo (Code Review) -
Lance Zhao (Code Review)
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Lean Sheng Tan (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)
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Subrata Banik (Code Review)