Lean Sheng Tan has uploaded this change for review.
mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP
This patch fixes display issues on both CFL-H & S, and WHL Intel RVP
platform where display are not showing up in UEFI shell, by configuring
DDi ports in device tree.
This patches also fixes no eDP display observed in UEFI shell on UEFI
Payload. Root cause is eDP requires minimum delay between GPIO programming
and eDP initialisation, which was not sufficient during FSP initialisation
which causes VBT to return error during eDP init.
This issue is fixed by programming eDP GPIO's in bootblock stage and skipping
FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree.
TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S &
WHL Intel RVP platforms.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c
---
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
4 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
index ec8f58b..aa009bb 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
@@ -593,6 +593,19 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
+ #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
+ /* I4 : EDP_HPD */
+ PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1),
+
+ /* F19 : EDP_VDDEN */
+ PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1),
+
+ /* F20 : EDP_BKLTEN */
+ PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1),
+
+ /* F21 : EDP_BKLTCTL */
+ PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1),
+ #endif
};
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
index 9648ac3..40da8eb 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb
@@ -9,6 +9,19 @@
register "RMT" = "1"
register "ScsEmmcHs400Enabled" = "1"
+ # Enable eDP device
+ register "DdiPortEdp" = "0"
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ register "DdiPortDHpd" = "1"
+ register "DdiPortFHpd" = "0"
+ # Enable DDC for DDI ports B/C
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "1"
+ register "DdiPortDDdc" = "1"
+ register "DdiPortFDdc" = "0"
+
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
index 126cab0..6ee52a4 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb
@@ -9,6 +9,19 @@
register "RMT" = "1"
register "ScsEmmcHs400Enabled" = "1"
+ # Enable eDP device
+ register "DdiPortEdp" = "0"
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ register "DdiPortDHpd" = "1"
+ register "DdiPortFHpd" = "1"
+ # Enable DDC for DDI ports B/C
+ register "DdiPortBDdc" = "0"
+ register "DdiPortCDdc" = "1"
+ register "DdiPortDDdc" = "1"
+ register "DdiPortFDdc" = "1"
+
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)"
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
index 429d5da..e824ac9 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb
@@ -9,6 +9,19 @@
register "ScsEmmcHs400Enabled" = "1"
register "HeciEnabled" = "1"
+ # Enable eDP device
+ register "DdiPortEdp" = "1"
+ # Enable HPD for DDI ports B/C
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "1"
+ register "DdiPortDHpd" = "0"
+ register "DdiPortFHpd" = "0"
+ # Enable DDC for DDI ports B/C
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "1"
+ register "DdiPortDDdc" = "1"
+ register "DdiPortFDdc" = "0"
+
# Enable eDP device
register "DdiPortEdp" = "1"
# Enable HPD for DDI ports B/C/D/F
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