Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
sb/intel/ibexpeak: Don't clear PMBASE regs in romstage
Boots fine without it.
Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 0 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35769/1
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 633bb21..8a75ae4 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -95,21 +95,6 @@ early_usb_init(mainboard_usb_ports); }
-static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - static void set_fsb_frequency(void) { u8 block[5]; @@ -180,20 +165,6 @@ outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee);
- write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index e2414bd..5f909d4 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -91,29 +91,6 @@ early_usb_init(mainboard_usb_ports); }
-static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - -// unused func - used for RE -#if 0 -static inline u16 read_acpi16(u32 addr) -{ - return inw(DEFAULT_PMBASE | addr); -} -#endif - void mainboard_romstage_entry(void) { u32 reg32; @@ -169,20 +146,6 @@ /* Enable SMBUS. */ enable_smbus();
- write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 1: Code-Review+1
Hello Alexander Couzens, Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35769
to look at the new patch set (#3).
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
sb/intel/ibexpeak: Don't clear PMBASE regs in romstage
Boots fine without it.
Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 0 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35769/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 6:
Is there common code clearing those bits? Why don't you need to clear it?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 6:
Patch Set 6:
Is there common code clearing those bits? Why don't you need to clear it?
No other Intel platform does that in romstage and this is likely here as a copy from disassembled vendor firmware or a SerialICE trace. Handling those is done by the code that sets up SMM.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 6: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35769/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35769/6//COMMIT_MSG@9 PS6, Line 9: Boots fine The X201?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35769/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35769/6//COMMIT_MSG@9 PS6, Line 9: Boots fine
The X201?
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
Patch Set 8: Code-Review+2
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35769 )
Change subject: sb/intel/ibexpeak: Don't clear PMBASE regs in romstage ......................................................................
sb/intel/ibexpeak: Don't clear PMBASE regs in romstage
X201 boots fine without it.
Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c 2 files changed, 0 insertions(+), 66 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 010ab86..65abc36 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -94,21 +94,6 @@ early_usb_init(mainboard_usb_ports); }
-static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - static void set_fsb_frequency(void) { u8 block[5]; @@ -179,20 +164,6 @@ outb(0x50, 0x15ec); outb(inb(0x15ee) & 0x70, 0x15ee);
- write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 2aeee1e..6cee711 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -90,29 +90,6 @@ early_usb_init(mainboard_usb_ports); }
-static inline void write_acpi32(u32 addr, u32 val) -{ - outl(val, DEFAULT_PMBASE | addr); -} - -static inline void write_acpi16(u32 addr, u16 val) -{ - outw(val, DEFAULT_PMBASE | addr); -} - -static inline u32 read_acpi32(u32 addr) -{ - return inl(DEFAULT_PMBASE | addr); -} - -// unused func - used for RE -#if 0 -static inline u16 read_acpi16(u32 addr) -{ - return inw(DEFAULT_PMBASE | addr); -} -#endif - void mainboard_romstage_entry(void) { u32 reg32; @@ -168,20 +145,6 @@ /* Enable SMBUS. */ enable_smbus();
- write_acpi16(0x2, 0x0); - write_acpi32(0x28, 0x0); - write_acpi32(0x2c, 0x0); - if (!s3resume) { - read_acpi32(0x4); - read_acpi32(0x20); - read_acpi32(0x34); - write_acpi16(0x0, 0x900); - write_acpi32(0x20, 0xffff7ffe); - write_acpi32(0x34, 0x56974); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, - pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); - } - early_thermal_init();
timestamp_add_now(TS_BEFORE_INITRAM);
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)