Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46249 )
Change subject: mb/clevo/l140cu: Correct FSP-M UPDs ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c:
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... PS1, Line 10: .spd_spec = {.spd_index = 0}, nit: this is redundant, as the non-initialized struct members default to zero
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... PS1, Line 25: These will typically be the following : * values for Cannon Lake : { 80, 40, 40, 40, 30 } Drop these
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... PS1, Line 31: Indicates whether memory is interleaved. : * Set to 1 for an interleaved design, : * set to 0 for non-interleaved design. https://i.imgur.com/eyvgl1S.jpeg
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... PS1, Line 38: * VREF_CA configuration. : * Set to 0 VREF_CA goes to both CH_A and CH_B, : * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, : * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. Replace this with something that explains the chosen value: https://review.coreboot.org/c/coreboot/+/37441/66/src/mainboard/supermicro/x...
https://review.coreboot.org/c/coreboot/+/46249/1/src/mainboard/clevo/cml-u/v... PS1, Line 45: /* Early Command Training */ Same here: https://review.coreboot.org/c/coreboot/+/37441/66/src/mainboard/supermicro/x...
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Angel Pons (Code Review)