5 comments:
File src/mainboard/clevo/cml-u/variants/l140cu/romstage.c:
Patch Set #1, Line 10: .spd_spec = {.spd_index = 0},
nit: this is redundant, as the non-initialized struct members default to zero
These will typically be the following
* values for Cannon Lake : { 80, 40, 40, 40, 30 }
Drop these
Indicates whether memory is interleaved.
* Set to 1 for an interleaved design,
* set to 0 for non-interleaved design.
https://i.imgur.com/eyvgl1S.jpeg
* VREF_CA configuration.
* Set to 0 VREF_CA goes to both CH_A and CH_B,
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
Replace this with something that explains the chosen value: https://review.coreboot.org/c/coreboot/+/37441/66/src/mainboard/supermicro/x11-lga1151v2-series/romstage.c
Patch Set #1, Line 45: /* Early Command Training */
Same here: https://review.coreboot.org/c/coreboot/+/37441/66/src/mainboard/supermicro/x11-lga1151v2-series/romstage.c
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