Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
Done using autoport and then a bunch of manual edits.
Working: - Two DIMMs - Serial port to emit spam - S3 suspend/resume - Some USB ports - Realtek GbE - Integrated graphics (libgfxinit) - HDMI and VGA - Some SATA ports - Native raminit - Flashing with flashrom
Untested: - Four DIMMs - PS/2 ports - Audio: Only rear output (green) has been tested - EHCI debug - PCIe ports (some need to be disabled) - PCI ports on the ASM1083 PCI bridge - The remaining ports - Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8z77-v_lx2/Kconfig A src/mainboard/asus/p8z77-v_lx2/Kconfig.name A src/mainboard/asus/p8z77-v_lx2/Makefile.inc A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8z77-v_lx2/board_info.txt A src/mainboard/asus/p8z77-v_lx2/devicetree.cb A src/mainboard/asus/p8z77-v_lx2/dsdt.asl A src/mainboard/asus/p8z77-v_lx2/early_init.c A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads A src/mainboard/asus/p8z77-v_lx2/gpio.c A src/mainboard/asus/p8z77-v_lx2/hda_verb.c 14 files changed, 634 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39299/1
diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig new file mode 100644 index 0000000..82310ab --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_V_LX2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8z77-v_lx2 + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-V LX2" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name new file mode 100644 index 0000000..0dec75f --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8Z77_V_LX2 + bool "P8Z77-V LX2" diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc new file mode 100644 index 0000000..7167e10 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl new file mode 100644 index 0000000..d8d3320 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c new file mode 100644 index 0000000..7f69572 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-v_lx2/board_info.txt new file mode 100644 index 0000000..79c36d6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb new file mode 100644 index 0000000..f564aee --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -0,0 +1,113 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1043 0x84ca inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # xHCI + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1: + device pci 1c.1 on end # RP #2: + device pci 1c.2 on end # RP #3: + device pci 1c.3 on end # RP #4: + device pci 1c.4 on end # RP #5: RTL8111 GbE NIC + device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge + device pci 1c.6 on end # RP #7: + device pci 1c.7 on end # RP #8: + + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl new file mode 100644 index 0000000..f164b33 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c new file mode 100644 index 0000000..a720c1f --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states. */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads new file mode 100644 index 0000000..37135f9 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, + Analog, + Others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-v_lx2/gpio.c new file mode 100644 index 0000000..634fb2e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gpio.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio28 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c new file mode 100644 index 0000000..a52ccfb --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39299
to look at the new patch set (#2).
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
Done using autoport and then a bunch of manual edits.
Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8z77-v_lx2/Kconfig A src/mainboard/asus/p8z77-v_lx2/Kconfig.name A src/mainboard/asus/p8z77-v_lx2/Makefile.inc A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8z77-v_lx2/board_info.txt A src/mainboard/asus/p8z77-v_lx2/devicetree.cb A src/mainboard/asus/p8z77-v_lx2/dsdt.asl A src/mainboard/asus/p8z77-v_lx2/early_init.c A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads A src/mainboard/asus/p8z77-v_lx2/gpio.c A src/mainboard/asus/p8z77-v_lx2/hda_verb.c 14 files changed, 634 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39299/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39299
to look at the new patch set (#3).
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
Done using autoport and then a bunch of manual edits.
Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8z77-v_lx2/Kconfig A src/mainboard/asus/p8z77-v_lx2/Kconfig.name A src/mainboard/asus/p8z77-v_lx2/Makefile.inc A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8z77-v_lx2/board_info.txt A src/mainboard/asus/p8z77-v_lx2/data.vbt A src/mainboard/asus/p8z77-v_lx2/devicetree.cb A src/mainboard/asus/p8z77-v_lx2/dsdt.asl A src/mainboard/asus/p8z77-v_lx2/early_init.c A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads A src/mainboard/asus/p8z77-v_lx2/gpio.c A src/mainboard/asus/p8z77-v_lx2/hda_verb.c 15 files changed, 635 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39299/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3: Code-Review+1
(7 comments)
Nice job!
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@7 PS3, Line 7: mb/asus/p8z77-v_lx2: Add new mainboard Add Sandy Bridge mainboard
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@27 PS3, Line 27: Add tested payload and OS?
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 18: */ Use official comment styles?
https://doc.coreboot.org/coding_style.html#commenting
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 20: Method(_PTS,1) Add space before the comma?
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 26: Method(_WAK,1) Ditot.
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 48: /* Select SIO pin states. */ Remove the dot/period at the end?
Are these from the datasheet or superiotool dump?
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 57: /* Power RAM in S3. */ Remove dot/period at end.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@7 PS3, Line 7: mb/asus/p8z77-v_lx2: Add new mainboard
Add Sandy Bridge mainboard
It's not sandy bridge though, it has an i5-3330 CPU
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 18: */
Use official comment styles? […]
This file was literally copied from here: https://github.com/coreboot/coreboot/blob/master/src/mainboard/asus/p8h61-m_...
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 48: /* Select SIO pin states. */
Remove the dot/period at the end? […]
Why?
The datasheet does not tell you which values the mainboard has to use, so I used superiotool.
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 57: /* Power RAM in S3. */
Remove dot/period at end.
Why?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 48: /* Select SIO pin states. */
Why? […]
It’s not needed in a comment, and for consistency (see below).
Thank you for the clarification.
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 57: /* Power RAM in S3. */
Why?
It’s not needed in a comment, and for consistency (see below).
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@7 PS3, Line 7: mb/asus/p8z77-v_lx2: Add new mainboard
It's not sandy bridge though, it has an i5-3330 CPU
Then Ivy Bridge.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@7 PS3, Line 7: mb/asus/p8z77-v_lx2: Add new mainboard
Then Ivy Bridge.
*replaces CPU with an i7-2600* Um, now it's not Ivy Bridge!
You know what? I'll just use the socket name: LGA1155 😄
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@27 PS3, Line 27:
Add tested payload and OS?
Oh, I thought I had that somewhere. In any case, it's SeaBIOS and Arch Linux
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 48: /* Select SIO pin states. */
It’s not needed in a comment, and for consistency (see below). […]
Ah, I see the inconsistency
Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Patrick Rudolph, Jonathan Kollasch, Paul Menzel, Arthur Heymans, Evgeny Zinoviev, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39299
to look at the new patch set (#4).
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits.
Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - SeaBIOS to boot Arch Linux
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/asus/p8z77-v_lx2/Kconfig A src/mainboard/asus/p8z77-v_lx2/Kconfig.name A src/mainboard/asus/p8z77-v_lx2/Makefile.inc A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8z77-v_lx2/board_info.txt A src/mainboard/asus/p8z77-v_lx2/data.vbt A src/mainboard/asus/p8z77-v_lx2/devicetree.cb A src/mainboard/asus/p8z77-v_lx2/dsdt.asl A src/mainboard/asus/p8z77-v_lx2/early_init.c A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads A src/mainboard/asus/p8z77-v_lx2/gpio.c A src/mainboard/asus/p8z77-v_lx2/hda_verb.c 15 files changed, 627 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39299/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 18: */
This file was literally copied from here: https://github. […]
Copied another file instead
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 20: Method(_PTS,1)
Add space before the comma?
Done
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 26: Method(_WAK,1)
Ditot.
Done (I guess this was meant to say "Ditto" ?) 😄
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 48: /* Select SIO pin states. */
Ah, I see the inconsistency
Done
https://review.coreboot.org/c/coreboot/+/39299/3/src/mainboard/asus/p8z77-v_... PS3, Line 57: /* Power RAM in S3. */
It’s not needed in a comment, and for consistency (see below).
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@7 PS3, Line 7: mb/asus/p8z77-v_lx2: Add new mainboard
*replaces CPU with an i7-2600* Um, now it's not Ivy Bridge! […]
Done
https://review.coreboot.org/c/coreboot/+/39299/3//COMMIT_MSG@27 PS3, Line 27:
Oh, I thought I had that somewhere. […]
Done
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 4: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 4: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 57: /* Power RAM in S3 */ Sorry, no that I have the datasheet, add “3VSBSW# enable bit” in the comment too?
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 63: /* Enable UART */ Either remove, as it’? obvious from `serial` in the function name, or *Enable UART A*.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 57: /* Power RAM in S3 */
Sorry, no that I have the datasheet, add “3VSBSW# enable bit” in the comment too?
The idea is that these comments provide a high-level explanation of what the code is doing. If somebody wants to know what this write to the ACPI device is exactly doing, they can check the datasheet.
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 63: /* Enable UART */
Either remove, as it’? obvious from `serial` in the function name, or *Enable UART A*.
There's no other UART on the board. As other boards have this comment (maybe not in the correct place, though), I would prefer to keep it.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... File src/mainboard/asus/p8z77-v_lx2/early_init.c:
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 57: /* Power RAM in S3 */
The idea is that these comments provide a high-level explanation of what the code is doing. […]
Ack
https://review.coreboot.org/c/coreboot/+/39299/4/src/mainboard/asus/p8z77-v_... PS4, Line 63: /* Enable UART */
There's no other UART on the board. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
mb/asus/p8z77-v_lx2: Add new mainboard
This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots. Porting was done using autoport and then doing a bunch of manual edits.
Working: - All four DIMM slots - Serial port to emit spam - PS/2 keyboard - S3 suspend/resume - Rear USB ports - Integrated graphics (libgfxinit) - HDMI and VGA - All PCIe ports - Realtek GbE (coreboot must set the MAC address) - Both PCI ports behind the ASM1083 PCI bridge - SATA ports - Native raminit - Flashing with flashrom - Rear audio output - VBT - SeaBIOS to boot Arch Linux
Untested: - PS/2 mouse - The other audio jacks - EHCI debug - Front USB headers - Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39299 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- A src/mainboard/asus/p8z77-v_lx2/Kconfig A src/mainboard/asus/p8z77-v_lx2/Kconfig.name A src/mainboard/asus/p8z77-v_lx2/Makefile.inc A src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl A src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl A src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl A src/mainboard/asus/p8z77-v_lx2/acpi_tables.c A src/mainboard/asus/p8z77-v_lx2/board_info.txt A src/mainboard/asus/p8z77-v_lx2/data.vbt A src/mainboard/asus/p8z77-v_lx2/devicetree.cb A src/mainboard/asus/p8z77-v_lx2/dsdt.asl A src/mainboard/asus/p8z77-v_lx2/early_init.c A src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads A src/mainboard/asus/p8z77-v_lx2/gpio.c A src/mainboard/asus/p8z77-v_lx2/hda_verb.c 15 files changed, 627 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig b/src/mainboard/asus/p8z77-v_lx2/Kconfig new file mode 100644 index 0000000..2041ce9 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig @@ -0,0 +1,44 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_V_LX2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select REALTEK_8168_RESET + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default asus/p8z77-v_lx2 + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-V LX2" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asus/p8z77-v_lx2/Kconfig.name b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name new file mode 100644 index 0000000..0dec75f --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8Z77_V_LX2 + bool "P8Z77-V LX2" diff --git a/src/mainboard/asus/p8z77-v_lx2/Makefile.inc b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc new file mode 100644 index 0000000..7167e10 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/Makefile.inc @@ -0,0 +1,7 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c + +romstage-y += early_init.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl new file mode 100644 index 0000000..b967f58 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/platform.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c new file mode 100644 index 0000000..7f69572 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-v_lx2/board_info.txt new file mode 100644 index 0000000..79c36d6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-v_lx2/data.vbt b/src/mainboard/asus/p8z77-v_lx2/data.vbt new file mode 100644 index 0000000..f8151e1 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb new file mode 100644 index 0000000..7ce2840 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -0,0 +1,112 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2020 Angel Pons th3fanbus@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0 on + subsystemid 0x1043 0x84ca inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIEX16_1 + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x000c0291" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + + device pci 14.0 on end # xHCI + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 on end # RP #1: PCIEX16_2 (electrical x4) + device pci 1c.1 off end # RP #2: + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: RTL8111 GbE NIC + device pci 1c.5 on end # RP #6: ASM1083 PCI Bridge + device pci 1c.6 on end # RP #7: PCIEX1_1 + device pci 1c.7 on end # RP #8: PCIEX1_2 + + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on end # GPIO0 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR Wake-up + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 off end # Port 80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asus/p8z77-v_lx2/dsdt.asl b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl new file mode 100644 index 0000000..f164b33 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-v_lx2/early_init.c new file mode 100644 index 0000000..c86dab7 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/early_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x70); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + pnp_write_config(GLOBAL_DEV, 0x22, 0xd7); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x48); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads new file mode 100644 index 0000000..37135f9 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gma-mainboard.ads @@ -0,0 +1,28 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI3, + Analog, + Others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-v_lx2/gpio.c new file mode 100644 index 0000000..634fb2e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/gpio.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio28 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c new file mode 100644 index 0000000..01bea72 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_lx2/hda_verb.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10438445), + AZALIA_PIN_CFG(0, 0x11, 0x99430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39299 )
Change subject: mb/asus/p8z77-v_lx2: Add new mainboard ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1179 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1178 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1177
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)