Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46288 )
Change subject: mb/google/puff/var/dooly: Update devicetree to remove unused devices ......................................................................
mb/google/puff/var/dooly: Update devicetree to remove unused devices
Remove unused device in Dooly no SD card reader no built-in LAN
BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status
Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 1 insertion(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46288/1
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 9d7cf1f..21bbc3c 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -149,9 +149,6 @@ }, }"
- # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" @@ -159,9 +156,6 @@ register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
- # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - # SATA port 1 Gen3 Strength # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB register "sata_port[1].TxGen3DeEmphEnable" = "1" @@ -304,6 +298,7 @@ end end end # USB xHCI + device pci 14.5 off end # SDCard device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 @@ -340,19 +335,6 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) register "PcieRpSlotImplemented[10]" = "1" end
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46288 )
Change subject: mb/google/puff/var/dooly: Update devicetree to remove unused devices ......................................................................
Patch Set 1: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46288 )
Change subject: mb/google/puff/var/dooly: Update devicetree to remove unused devices ......................................................................
mb/google/puff/var/dooly: Update devicetree to remove unused devices
Remove unused device in Dooly no SD card reader no built-in LAN
BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status
Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang tony-huang@quanta.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 1 insertion(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 9d7cf1f..21bbc3c 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -149,9 +149,6 @@ }, }"
- # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" @@ -159,9 +156,6 @@ register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0"
- # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - # SATA port 1 Gen3 Strength # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB register "sata_port[1].TxGen3DeEmphEnable" = "1" @@ -304,6 +298,7 @@ end end end # USB xHCI + device pci 14.5 off end # SDCard device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 @@ -340,19 +335,6 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) register "PcieRpSlotImplemented[10]" = "1" end