Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43231 )
Change subject: nb/intel/ironlake/raminit.c: Drop dead code ......................................................................
nb/intel/ironlake/raminit.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43231/1
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 13f0c35..017951c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3652,12 +3652,6 @@ MCHBAR8(0x2ca8) = 0; system_reset(); } -#if 0 - if (!s3resume) { - pre_raminit_3(x2ca8); - } - pre_raminit_4a(x2ca8); -#endif
dmi_setup();
@@ -3851,10 +3845,6 @@ collect_system_info(&info); calculate_timings(&info);
-#if 0 - pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); -#endif - if (!s3resume) { u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) {
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43231
to look at the new patch set (#2).
Change subject: nb/intel/ironlake/raminit.c: Drop dead code ......................................................................
nb/intel/ironlake/raminit.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43231/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43231 )
Change subject: nb/intel/ironlake/raminit.c: Drop dead code ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43231 )
Change subject: nb/intel/ironlake/raminit.c: Drop dead code ......................................................................
nb/intel/ironlake/raminit.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 13f0c35..f1f8aa5 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3652,12 +3652,6 @@ MCHBAR8(0x2ca8) = 0; system_reset(); } -#if 0 - if (!s3resume) { - pre_raminit_3(x2ca8); - } - pre_raminit_4a(x2ca8); -#endif
dmi_setup();
@@ -3851,10 +3845,6 @@ collect_system_info(&info); calculate_timings(&info);
-#if 0 - pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); -#endif - if (!s3resume) { u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) { @@ -4583,7 +4573,6 @@ MCHBAR8_OR(0xff4, 0x2); MCHBAR32_AND_OR(0xff8, ~0xe008, 0x1020);
-#if 1 MCHBAR32(0xd00) = IOMMU_BASE2 | 1; MCHBAR32(0xd40) = IOMMU_BASE1 | 1; MCHBAR32(0xdc0) = IOMMU_BASE4 | 1; @@ -4592,18 +4581,6 @@ write32p(IOMMU_BASE2 | 0xffc, 0xc0000000); write32p(IOMMU_BASE4 | 0xffc, 0x80000000);
-#else - { - u32 eax; - // = 0xe911714b - eax = read32p(0xffc + (MCHBAR32(0xd00) & ~1)) | 0x08000000; - write32p(0xffc + (MCHBAR32(0xd00) & ~1), eax); - // = 0xe911714b - eax = read32p(0xffc + (MCHBAR32(0xdc0) & ~1)) | 0x40000000; - write32p(0xffc + (MCHBAR32(0xdc0) & ~1), eax); - } -#endif - { u32 eax;
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)