Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 26 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/1
diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..c75b1e44 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,5 +16,13 @@ car_mtrr_mask: .uintptr_t _car_mtrr_mask
+car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start + +#if !CONFIG(NO_XIP_EARLY_STAGES) +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask +#endif diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..5d6994f 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -6,6 +6,8 @@
.global bootblock_pre_c_entry
+#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup:
@@ -91,7 +93,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -118,8 +120,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl
@@ -133,12 +135,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -156,6 +158,16 @@ andl $0xfffffff0, %esp subl $4, %esp
+#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -163,6 +175,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
before_c_entry: post_code(0x29)
Hello Patrick Georgi, Martin Roth, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45823
to look at the new patch set (#2).
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Tested on Lenovo T500 with additional patches.
Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 26 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 2: Code-Review+1
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 2: Code-Review+2
Attention is currently required from: Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45823
to look at the new patch set (#3).
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Tested on Lenovo T500 with additional patches.
Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 21 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/3
Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45823 )
Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ......................................................................
cpu/intel/car/core2/cache_as_ram: Add x86_64 support
Tested on Lenovo T500 with additional patches.
Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 21 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 2d2f4bd..0e5fdc3 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,6 +16,9 @@ car_mtrr_mask: .uintptr_t _car_mtrr_mask
+car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 2c67207..f47ba5f 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -7,6 +7,8 @@ .section .init .global bootblock_pre_c_entry
+#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup:
@@ -92,7 +94,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -119,8 +121,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl
@@ -134,12 +136,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr
@@ -157,6 +159,16 @@ andl $0xfffffff0, %esp subl $4, %esp
+#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -164,6 +176,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
before_c_entry: post_code(0x29)
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)
-
Patrick Rudolph (Code Review)