Change in coreboot[master]: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44351 )
Change subject: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug ......................................................................
soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges.
Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44351/1
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3f26a29..4415615 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,6 +104,9 @@ */ static int espi_std_io_decode(uint16_t base, size_t size) { + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; + if (size != 1) return -1;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44351 )
Change subject: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44351 )
Change subject: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug ......................................................................
soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges.
Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3f26a29..4415615 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,6 +104,9 @@ */ static int espi_std_io_decode(uint16_t base, size_t size) { + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; + if (size != 1) return -1;
-
Felix Held (Code Review) -
Furquan Shaikh (Code Review)