Jingle Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table and initialize ......................................................................
mb/ocp/monolake: Add GPIO table and initialize
Add GPIO table for Monolake to initialize GPIOs. Tested on Monolake
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/1
diff --git a/src/mainboard/ocp/monolake/gpio.h b/src/mainboard/ocp/monolake/gpio.h new file mode 100644 index 0000000..982daa4 --- /dev/null +++ b/src/mainboard/ocp/monolake/gpio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#ifndef MONOLAKE_GPIO_H +#define MONOLAKE_GPIO_H + +static const struct gpio_config gpio_tables[] = { + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + +#endif diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..d7f2c3a 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +#include "gpio.h"
/* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -59,6 +61,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); }
/*
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table and initialize ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@9 PS1, Line 9: Add GPIO table for Monolake to initialize GPIOs. why?
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@10 PS1, Line 10: Tested on Monolake how?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 66: init_gpios(gpio_tables); why here and not in ramstage or early_romstage?
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table and initialize ......................................................................
Patch Set 1:
Patch Set 1:
(3 comments)
Hello Patrick Rudolph, Jonathan Zhang, Johnny Lin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35367
to look at the new patch set (#2).
Change subject: mb/ocp/monolake: Add a GPIO table for initializing configuration ......................................................................
mb/ocp/monolake: Add a GPIO table for initializing configuration
Add a GPIO table for Monolake to initialize GPIOs. Tested on Monolake
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/2
Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing configuration ......................................................................
Patch Set 2:
(3 comments)
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@9 PS1, Line 9: Add GPIO table for Monolake to initialize GPIOs.
why?
We simply want to have a gpio table that can be configured in a centrally managed way.
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@10 PS1, Line 10: Tested on Monolake
how?
Verified by using ITP to check the configurations
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 66: init_gpios(gpio_tables);
why here and not in ramstage or early_romstage?
We initialize GPIOs when fsp setup_gpio_io_address() finished, which is after early_romstage.
Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/gpio.h:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 50: 28 in follow up patch, could you please provide string literals for these numbers that are actually used for something? it would be helpful to understand what pin 28 is used for and why we are setting it to native mode. e.g: {SPI0_CS_N, GPIO_MODE_NATIVE, 0, 0, 0, 0}
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing configuration ......................................................................
Patch Set 2: Code-Review-1
(1 comment)
Thanks for doing this, Jingle. I started reviewing some of the GPIOs and may have questions tomorrow :-)
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/gpio.h:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 21: static const struct gpio_config gpio_tables[] = { Header files are generally only used for declarations. Since this is a definition it should go in a source file (e.g. romstage.c).
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing configuration ......................................................................
Patch Set 2:
(14 comments)
I went thru the GPIO listing and have a few questions, particular concerning the MGPIOs, SATA pins, and OC pins.
Some GPIOs listed don't seem to exist. It should be safe to set them as inputs as you have done, I just wanted to note them in case we're looking at different schematics/datasheets.
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/gpio.h:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 31: {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, GPIO9 and GPIO10 are overcurrent indicators, should they be left in native function (default) state?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 36: {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, GPIO14 is an overcurrent indicators, should it be left in native function (default) state?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 46: {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, I think this is acting as MGPIO0?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 50: {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, I think GPIO27 and GPIO28 are acting as MGPIO6 and MGPIO7?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 53: {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, I think this is acting as MGPIO2?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 56: {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, Oddly enough I don't even see GPIO34 mentioned in schematic, EDS, or other datasheets...
Anyway, it should be safe to set this as an input as you have done here. I'm just curious what, if anything, this should connect to.
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 61: {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, Should SATA0GP (GPIO21) be set to native function as well?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 65: {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, GPIO40-43 are overcurrent indicators, should they be left in default (native function) state?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 69: {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, Same as GPIO34 - This pin doesn't seem to really exist... Should be safe to set it as an input in any case.
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 78: {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, Another missing GPIO (like 47 and 34)?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 79: {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, I think this is acting as MGPIO5 (configured and driven by ME)?
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 86: {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, GPIOs 63 and 64 don't seem to exist? (Should be safe to set as inputs as you are doing...)
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 88: {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, Another missing one...
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 95: {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, Another phantom GPIO...
Hello Patrick Rudolph, Jonathan Zhang, Johnny Lin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35367
to look at the new patch set (#3).
Change subject: mb/ocp/monolake: Add a GPIO table for initializing custom configurations ......................................................................
mb/ocp/monolake: Add a GPIO table for initializing custom configurations
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations.
Tested on Monolake
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing custom configurations ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 64: {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* H_BDXDE_PROCHOT_DISABLE */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 68: {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* PD_DMI_RX_TERMINATION */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 81: {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* FM_BIOS_POST_CMPLT_N */ line over 96 characters
Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing custom configurations ......................................................................
Patch Set 3:
Patch Set 2:
(14 comments)
I went thru the GPIO listing and have a few questions, particular concerning the MGPIOs, SATA pins, and OC pins.
Some GPIOs listed don't seem to exist. It should be safe to set them as inputs as you have done, I just wanted to note them in case we're looking at different schematics/datasheets.
Your gpio findings are correct with our schematics. We configure these gpios by following the proprietary UEFI BIOS configurations, after comparing the ITP gpio dump they are the same after applying this change.
Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing custom configurations ......................................................................
Patch Set 3:
(2 comments)
Patch Set 2:
(14 comments)
I went thru the GPIO listing and have a few questions, particular concerning the MGPIOs, SATA pins, and OC pins.
Some GPIOs listed don't seem to exist. It should be safe to set them as inputs as you have done, I just wanted to note them in case we're looking at different schematics/datasheets.
Your gpio findings are correct with our schematics. We configure these gpios by following the proprietary UEFI BIOS configurations, after comparing the ITP gpio dump they are the same after applying this change.
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/gpio.h:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 21: static const struct gpio_config gpio_tables[] = {
Header files are generally only used for declarations. […]
Done
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 50: 28
in follow up patch, could you please provide string literals for these numbers that are actually use […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add a GPIO table for initializing custom configurations ......................................................................
Patch Set 3:
(2 comments)
Welcome to coreboot!
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG@7 PS3, Line 7: mb/ocp/monolake: Add a GPIO table for initializing custom configurations Shorter?
Add GPIO table to initialize custom configs
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG@10 PS3, Line 10: with custom board configurations. Please use the full text width of 75 characters.
Hello Patrick Rudolph, Jonathan Zhang, Johnny Lin, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Andrey Petrov,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35367
to look at the new patch set (#4).
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
mb/ocp/monolake: Add GPIO table to initialize custom configs
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations.
Tested on Monolake.
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 86 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/4
Jingle Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG@7 PS3, Line 7: mb/ocp/monolake: Add a GPIO table for initializing custom configurations
Shorter? […]
Done
https://review.coreboot.org/c/coreboot/+/35367/3//COMMIT_MSG@10 PS3, Line 10: with custom board configurations.
Please use the full text width of 75 characters.
Done
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 4: Code-Review+1
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 4: Code-Review+2
Thanks, Jingle!
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 64: {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* H_BDXDE_PROCHOT_DISABLE */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 68: {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* PD_DMI_RX_TERMINATION */ line over 96 characters
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 81: {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* FM_BIOS_POST_CMPLT_N */ line over 96 characters
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 5:
(20 comments)
BTW, we recently started requiring that all comments are resolved prior to a patch being merged. I went ahead and marked all comments as such, though I'm not 100% sure about the lint warning (>96 characters on some lines, which is due to responding to a reviewer request).
I've asked others about the column width, and will merge this patch if they're OK with it.
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@9 PS1, Line 9: Add GPIO table for Monolake to initialize GPIOs.
We simply want to have a gpio table that can be configured in a centrally managed way.
Ack
https://review.coreboot.org/c/coreboot/+/35367/1//COMMIT_MSG@10 PS1, Line 10: Tested on Monolake
Verified by using ITP to check the configurations
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/gpio.h:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 31: {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
GPIO9 and GPIO10 are overcurrent indicators, should they be left in native function (default) state?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 36: {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
GPIO14 is an overcurrent indicators, should it be left in native function (default) state?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 46: {24, GPIO_MODE_NATIVE, 0, 0, 0, 0},
I think this is acting as MGPIO0?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 50: {28, GPIO_MODE_NATIVE, 0, 0, 0, 0},
I think GPIO27 and GPIO28 are acting as MGPIO6 and MGPIO7?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 53: {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
I think this is acting as MGPIO2?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 56: {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
Oddly enough I don't even see GPIO34 mentioned in schematic, EDS, or other datasheets... […]
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 61: {39, GPIO_MODE_NATIVE, 0, 0, 0, 0},
Should SATA0GP (GPIO21) be set to native function as well?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 65: {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
GPIO40-43 are overcurrent indicators, should they be left in default (native function) state?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 69: {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
Same as GPIO34 - This pin doesn't seem to really exist... […]
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 78: {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
Another missing GPIO (like 47 and 34)?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 79: {57, GPIO_MODE_NATIVE, 0, 0, 0, 0},
I think this is acting as MGPIO5 (configured and driven by ME)?
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 86: {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
GPIOs 63 and 64 don't seem to exist? (Should be safe to set as inputs as you are doing... […]
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 88: {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
Another missing one...
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 95: {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0},
Another phantom GPIO...
Ack
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/1/src/mainboard/ocp/monolake/... PS1, Line 66: init_gpios(gpio_tables);
We initialize GPIOs when fsp setup_gpio_io_address() finished, […]
Ack
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 64: {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* H_BDXDE_PROCHOT_DISABLE */
line over 96 characters
Ack. The comment was added in response to reviewer feedback.
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 68: {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* PD_DMI_RX_TERMINATION */
line over 96 characters
Ack. The comment was added in response to reviewer feedback.
https://review.coreboot.org/c/coreboot/+/35367/5/src/mainboard/ocp/monolake/... PS5, Line 81: {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* FM_BIOS_POST_CMPLT_N */
line over 96 characters
Ack. The comment was added in response to reviewer feedback.
David Hendricks has uploaded a new patch set (#6) to the change originally created by Jingle Hsu. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
mb/ocp/monolake: Add GPIO table to initialize custom configs
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations.
Tested on Monolake.
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 162 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/6
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 6: Code-Review+2
I got some advice from another member in the community to interleave comments and code to avoid hitting the line width limit. In the interest of time I went ahead and implemented that suggestion so we can hopefully get this patch merged soon.
David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 6:
(3 comments)
marking some more comments as resolved...
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 64: {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* H_BDXDE_PROCHOT_DISABLE */
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 68: {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* PD_DMI_RX_TERMINATION */
line over 96 characters
Done
https://review.coreboot.org/c/coreboot/+/35367/3/src/mainboard/ocp/monolake/... PS3, Line 81: {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, /* FM_BIOS_POST_CMPLT_N */
line over 96 characters
Done
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 6: Code-Review+2
Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
mb/ocp/monolake: Add GPIO table to initialize custom configs
Add a GPIO table for Monolake to initialize GPIOs with custom board configurations.
Tested on Monolake.
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35367 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: David Hendricks david.hendricks@gmail.com Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com --- M src/mainboard/ocp/monolake/romstage.c 1 file changed, 162 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved
diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..ef41b77 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Wiwynn Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,10 +25,168 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +
/* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading"
+static const struct gpio_config gpio_tables[] = { + /* PU_BMBUSY_N */ + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SKU_BDE_ID1 */ + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ERR0_LVT3_N */ + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ERR1_LVT3_N */ + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPU2PCH_THROT_LVT3 */ + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_CATERR_LVT3_N */ + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SKU_BDE_ID2 */ + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* REV_BDE_ID0 */ + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RQ_BMC_PCH_NMI_NOA1_CLK */ + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_5_N */ + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_6_N */ + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_SMBALERT_N */ + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RQ_IBMC_PCH_SMI_LPC_N */ + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_LVC3_RISER1_ID4_N_PU */ + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_P1V2_VDDQ_SEL_N */ + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPU_THROTTLE_N */ + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* SKU_BDE_ID0 */ + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_SRC1CLKRQB */ + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* RST_PCIE_PCH_N */ + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SMI_BMC_N_R */ + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* M_SATA0GP */ + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SGPIO_SATA_CLOCK_R */ + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* TP */ + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FAST_THROTTLE_N_R */ + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* BMC_READY_N */ + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_CPLD */ + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BDXDE_ME_DRIVE_N */ + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* H_BDXDE_PROCHOT_DISABLE */ + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* SUSPWRDNACK */ + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SMB_INA230_ALRT_N */ + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_DMI_RX_TERMINATION */ + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* NC */ + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NMI_BDE_R */ + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_BIOS_ADV_FUNCTIONS */ + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_ADR_TRIGGER_N */ + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* SGPIO_SATA_LOAD_R */ + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SGPIO_SATA_DATAOUT0_R */ + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_USB_OC_1_N */ + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_2_N */ + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_3_N */ + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_USB_OC_4_N */ + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TP */ + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_BIOS_POST_CMPLT_N */ + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + /* NC */ + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_SGPIO_SATA_DATAOUT1 */ + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* FM_XDP_PCH_OBSDATA */ + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXCLK */ + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXDOUT */ + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_CPUSV */ + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PD_GSXDIN */ + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_GSXSREST_N */ + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_BIOS_RCVR_BOOT_J2 */ + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_ME_RCVR_N */ + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML1_3V3SB_CLK */ + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* FM_USB_OC_0_N */ + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML0_3V3SB_ALERT */ + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SLP_SUS_STAT_N */ + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* CLK_CPLD_SUSCLK_R */ + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* NC */ + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* REV_BDE_ID1 */ + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* TPM_PRSNT_N */ + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PU_BATLOW_N */ + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* NC */ + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + /* PCHHOT_CPU_N */ + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + /* SMB_SML1_3V3SB_DAT */ + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + /** * /brief mainboard call for setup that needs to be done before fsp init * @@ -59,6 +218,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); }
/*
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 7:
Patch Set 6:
(3 comments)
marking some more comments as resolved...
Hi David, Thanks for your patchset! Noted the width limit and will avoid that in the future.
Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table to initialize custom configs ......................................................................
Patch Set 7:
Patch Set 6:
(3 comments)
marking some more comments as resolved...
Hi David, Thanks for your patchset! Noted the width limit and will avoid that.
-
Andrey Petrov (Code Review) -
build bot (Jenkins) (Code Review)
-
David Hendricks (Code Review)
-
Jingle Hsu (Code Review)
-
Johnny Lin (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)
-
Philipp Deppenwiese (Code Review)