Change in coreboot[master]: [WIP] soc/intel: Replace config_of_path() with config_of_soc()
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: [WIP] soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
[WIP] soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure.
Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/device.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/fsp_broadwell_de/iou_complto.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c 46 files changed, 72 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35656/1
diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221cc..74e574b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -314,16 +314,9 @@ devtree_die(); }
-static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) +static inline DEVTREE_CONST void *config_of_soc(void) { - const struct device *dev = pcidev_path_on_root(devfn); - if (dev) - return config_of(dev); - - devtree_bug(__func__, devfn); - - dev = dev_find_slot(0, devfn); - return config_of(dev); + return config_of(pcidev_on_root(0, 0)); }
void scan_smbus(struct device *bus); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6b3423b..89e6927 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -221,7 +221,7 @@
static void mainboard_enable(struct device *dev) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
mainboard_set_power_limits(conf);
diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 0717e81..c648a52 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -23,7 +23,7 @@ uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 6cd017b..1e1d083 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -23,7 +23,7 @@ uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 9c4b2bc..e1538c6 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -39,7 +39,7 @@ /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e48a952..e3855bd 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -241,7 +241,7 @@ uint8_t pl2_id = PL2_ID_DEFAULT; struct device *spi_fpmcu = PCH_DEV_GSPI1;
- config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
switch (sku_id) { case SKU_0_SONA: diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 9aa6b72..b78ec82 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -44,7 +44,7 @@ uint16_t abase; uint32_t val32;
- config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
switch (sku_id) { case SKU_0_NAUTILUS: diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 7b6b28b..3743cf7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -40,7 +40,7 @@ /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index f729f31..7163884 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -90,7 +90,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
/* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -152,7 +152,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b69f9ee..ddbe734 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -300,7 +300,7 @@ uint32_t tdp, min_power, max_power; uint32_t pl2_val;
- cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); @@ -364,7 +364,7 @@ struct soc_intel_apollolake_config *cfg; uint32_t scis;
- cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
/* Change only if a device tree entry exists. */ if (cfg->sci_irq) { diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3f06026..3349627 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -296,7 +296,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 905fa64..77711eb 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 84b61da..23e9732 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -148,7 +148,7 @@ { DEVTREE_CONST struct soc_intel_apollolake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw1; diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index 0e9e931..274f630 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -39,7 +39,7 @@ const struct pnpconfig *pnpconfigarr; struct soc_intel_apollolake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
switch (config->pnp_settings) { case PNP_PERF: diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2949865..8418919 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void configure_thermal_target(void) { msr_t msr; - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc();
if (!conf->tcc_offset) return; @@ -269,7 +269,7 @@ /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- const config_t *config = config_of_path(PCH_DEVFN_LPC); + const config_t *config = config_of_soc();
m_cfg->PrmrrSize = config->PrmrrSize;
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc00..7acde68 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -390,7 +390,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (config->s0ix_enable) set = cstate_set_s0ix; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 54a695e..8fe66dc 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -196,7 +196,7 @@
static void initialize_vr_config(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -450,7 +450,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 0bd4ccd..af8ea53 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -78,7 +78,7 @@ /* Lookup device tree in romstage */ const config_t *config;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 89770c0..6846594 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -145,7 +145,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
@@ -166,7 +166,7 @@
void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Generate P-state tables */ if (config->eist_enable) @@ -177,7 +177,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -202,7 +202,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4e0dba5..47e01a4 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -170,7 +170,7 @@ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0f4d52e..c58b9ad 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -106,7 +106,7 @@ unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -234,7 +234,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
if (conf->speed_shift_enable) { @@ -259,7 +259,7 @@
static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); @@ -361,7 +361,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
/* Set TCC activation offset if supported */ @@ -387,7 +387,7 @@ const struct soc_intel_cannonlake_config *config; msr_t msr;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */ if (!config->PmTimerDisabled) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index c99653b..115b732 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -84,7 +84,7 @@ * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 76d40aa..b580620 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -99,7 +99,7 @@
static void parse_devicetree(FSP_S_CONFIG *params) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
parse_devicetree_param(config, params); } @@ -145,7 +145,7 @@ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index b9f455f..c0bb9ae 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -102,7 +102,7 @@
static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
rtc_init();
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 1626e30..a543861 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -175,7 +175,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index b8ceec0..4d0b241 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -79,7 +79,7 @@ { const struct soc_intel_cannonlake_config *config;
- config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 9e74803..5ab8f6b 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -22,7 +22,7 @@ const struct soc_intel_common_config *soc_config; const config_t *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_config = &config->common_soc_config;
return soc_config; diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index f998d97..b092f53 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -24,7 +24,7 @@ static void iou_init(struct device *dev) { /* Use config from device always present in static devicetree. */ - const config_t *config = config_of_path(SOC_DEV_FUNC); + const config_t *config = config_of_soc(); u16 devctl2;
/* pcie completion timeout diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index c61d877..4089679 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -138,7 +138,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
@@ -159,7 +159,7 @@
void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (config->eist_enable) /* Generate P-state tables */ @@ -170,7 +170,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -194,7 +194,7 @@
void acpi_create_gnvs(struct global_nvs_t *gnvs) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index c4abb0c..951e1d2 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -107,7 +107,7 @@ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 8a65ccf..0ecccb9 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -40,7 +40,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
if (conf->speed_shift_enable) { @@ -67,7 +67,7 @@ { msr_t msr;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 086787d..a70b5a1 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -83,7 +83,7 @@ * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e31e47b..8819e7d 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -31,7 +31,7 @@ static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; @@ -69,7 +69,7 @@
struct device *dev; struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 28fc01d..6348d28 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -84,7 +84,7 @@
static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
rtc_init();
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index a70840b..c20da50 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -174,7 +174,7 @@ { DEVTREE_CONST struct soc_intel_icelake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a4..5bf3421 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -79,7 +79,7 @@ const struct soc_intel_icelake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 8db2c3b..b7c37d4 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -76,7 +76,7 @@ { const struct soc_intel_icelake_config *config;
- config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a64fed4..cd654d7 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -93,7 +93,7 @@ "Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */ - config = config_of_path(LPC_DEV_FUNC); + config = config_of_soc();
/* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c3757b0..43f9c39 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -172,7 +172,7 @@
static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; @@ -232,7 +232,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); @@ -503,7 +503,7 @@ int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", @@ -674,7 +674,7 @@ /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f..9d27a0f0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -237,7 +237,7 @@ uintptr_t vbt_data = (uintptr_t)vbt_get(); int i;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..5424c91 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -240,7 +240,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -260,7 +260,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -286,7 +286,7 @@
static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -562,7 +562,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe0605..ab9297f 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -188,7 +188,7 @@ */ static void pm1_handle_wake_pin(void *unused) { - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc();
/* If WAKE# pin is enabled, bail out early. */ if (conf->deep_sx_config & DSX_EN_WAKE_PIN) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b03..329cea9 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -177,7 +177,7 @@ { DEVTREE_CONST struct soc_intel_skylake_config *config;
- config = config_of_path(PCH_DEVFN_PMC); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a8bbfb6..f354af3 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -43,7 +43,7 @@ /* Program MCHBAR and DMIBAR */ systemagent_early_init();
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* Force a full memory train if RMT is enabled */ params->disable_saved_data = config->Rmt; @@ -57,7 +57,7 @@
/* Set the parameters for MemoryInit */
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index deda533..af89441 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -289,7 +289,7 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..bf0d506 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -29,7 +29,7 @@ const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); if (config->ignore_vtd) return;
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: [WIP] soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 1:
I am not 100% sure if I jumped the correct conclusions here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: [WIP] soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h... PS1, Line 317: static inline DEVTREE_CONST void *config_of_soc(void) : { : return config_of(pcidev_on_root(0, 0)); : } Overall the change looks good to me. I am just wondering if this function should be put under soc/intel/common since: 1. config_of_path()/config_of_soc() is used by only soc/intel/... and mainboards using those SoCs 2. pcidev_on_root(0, 0) for getting to this config is kind of true for only soc/intel/... It doesn't seem to be true for boards with northbridge/southbridge for example.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: [WIP] soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 1:
(1 comment)
Richard, Marshall: Accessing dev->chip_info should be cleaned up under soc/amd.
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h... PS1, Line 317: static inline DEVTREE_CONST void *config_of_soc(void) : { : return config_of(pcidev_on_root(0, 0)); : }
Overall the change looks good to me. […]
Right... I think we can find different way to find top-level .chip_info, so implementation would not depend on PCI 0:0.0 and becomes usable for soc/amd as well.
Platforms with separate cpu/,nb/,sb/ could not use config_of_soc() anyways, but config_of(dev) instead. The configuration structures are split like the directories.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: [WIP] soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 3: Code-Review+1
remove the [wip] ?
Hello Aaron Durbin, Patrick Rudolph, Subrata Banik, Marshall Dawson, Richard Spiegel, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35656
to look at the new patch set (#4).
Change subject: soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure.
Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/device.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/fsp_broadwell_de/iou_complto.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c 46 files changed, 72 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/35656/4
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 4: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h File src/include/device/device.h:
https://review.coreboot.org/c/coreboot/+/35656/1/src/include/device/device.h... PS1, Line 317: static inline DEVTREE_CONST void *config_of_soc(void) : { : return config_of(pcidev_on_root(0, 0)); : }
Right... I think we can find different way to find top-level . […]
We'll revisit this if we come across an (AMD) platform where it would not work.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
soc/intel: Replace config_of_path() with config_of_soc()
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure.
Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/include/device/device.h M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/fsp_broadwell_de/iou_complto.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c 46 files changed, 72 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/include/device/device.h b/src/include/device/device.h index f24e4b2..cb37c09 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -321,16 +321,9 @@ devtree_die(); }
-static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) +static inline DEVTREE_CONST void *config_of_soc(void) { - const struct device *dev = pcidev_path_on_root(devfn); - if (dev) - return config_of(dev); - - devtree_bug(__func__, devfn); - - dev = dev_find_slot(0, devfn); - return config_of(dev); + return config_of(pcidev_on_root(0, 0)); }
void scan_smbus(struct device *bus); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6b3423b..89e6927 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -221,7 +221,7 @@
static void mainboard_enable(struct device *dev) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
mainboard_set_power_limits(conf);
diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 0717e81..c648a52 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -23,7 +23,7 @@ uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 6cd017b..1e1d083 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -23,7 +23,7 @@ uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 9c4b2bc..e1538c6 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -39,7 +39,7 @@ /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e48a952..e3855bd 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -241,7 +241,7 @@ uint8_t pl2_id = PL2_ID_DEFAULT; struct device *spi_fpmcu = PCH_DEV_GSPI1;
- config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
switch (sku_id) { case SKU_0_SONA: diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 9aa6b72..b78ec82 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -44,7 +44,7 @@ uint16_t abase; uint32_t val32;
- config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
switch (sku_id) { case SKU_0_NAUTILUS: diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 7b6b28b..3743cf7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -40,7 +40,7 @@ /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc();
/* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index f729f31..7163884 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -90,7 +90,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
/* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -152,7 +152,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b7159ef..8e516f8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -300,7 +300,7 @@ uint32_t tdp, min_power, max_power; uint32_t pl2_val;
- cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); @@ -364,7 +364,7 @@ struct soc_intel_apollolake_config *cfg; uint32_t scis;
- cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc();
/* Change only if a device tree entry exists. */ if (cfg->sci_irq) { diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3f06026..3349627 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -296,7 +296,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 905fa64..77711eb 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ if (!CONFIG(SOC_INTEL_GLK)) return tolum;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 84b61da..23e9732 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -148,7 +148,7 @@ { DEVTREE_CONST struct soc_intel_apollolake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw1; diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index 0e9e931..274f630 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -39,7 +39,7 @@ const struct pnpconfig *pnpconfigarr; struct soc_intel_apollolake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
switch (config->pnp_settings) { case PNP_PERF: diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2949865..8418919 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void configure_thermal_target(void) { msr_t msr; - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc();
if (!conf->tcc_offset) return; @@ -269,7 +269,7 @@ /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- const config_t *config = config_of_path(PCH_DEVFN_LPC); + const config_t *config = config_of_soc();
m_cfg->PrmrrSize = config->PrmrrSize;
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc00..7acde68 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -390,7 +390,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (config->s0ix_enable) set = cstate_set_s0ix; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 54a695e..8fe66dc 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -196,7 +196,7 @@
static void initialize_vr_config(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -450,7 +450,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 0bd4ccd..af8ea53 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -78,7 +78,7 @@ /* Lookup device tree in romstage */ const config_t *config;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 89770c0..6846594 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -145,7 +145,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
@@ -166,7 +166,7 @@
void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Generate P-state tables */ if (config->eist_enable) @@ -177,7 +177,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -202,7 +202,7 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index c0810fb..0ce2f1a 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -170,7 +170,7 @@ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0f4d52e..c58b9ad 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -106,7 +106,7 @@ unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -234,7 +234,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
if (conf->speed_shift_enable) { @@ -259,7 +259,7 @@
static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); @@ -361,7 +361,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
/* Set TCC activation offset if supported */ @@ -387,7 +387,7 @@ const struct soc_intel_cannonlake_config *config; msr_t msr;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */ if (!config->PmTimerDisabled) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index c99653b..115b732 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -84,7 +84,7 @@ * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 76d40aa..b580620 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -99,7 +99,7 @@
static void parse_devicetree(FSP_S_CONFIG *params) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
parse_devicetree_param(config, params); } @@ -145,7 +145,7 @@ FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index b9f455f..c0bb9ae 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -102,7 +102,7 @@
static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
rtc_init();
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 1626e30..a543861 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -175,7 +175,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index b8ceec0..4d0b241 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -79,7 +79,7 @@ { const struct soc_intel_cannonlake_config *config;
- config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 9e74803..5ab8f6b 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -22,7 +22,7 @@ const struct soc_intel_common_config *soc_config; const config_t *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_config = &config->common_soc_config;
return soc_config; diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index f998d97..b092f53 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -24,7 +24,7 @@ static void iou_init(struct device *dev) { /* Use config from device always present in static devicetree. */ - const config_t *config = config_of_path(SOC_DEV_FUNC); + const config_t *config = config_of_soc(); u16 devctl2;
/* pcie completion timeout diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index c61d877..4089679 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -138,7 +138,7 @@ int *set; int i;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
int is_s0ix_enable = config->s0ix_enable;
@@ -159,7 +159,7 @@
void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (config->eist_enable) /* Generate P-state tables */ @@ -170,7 +170,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS;
- config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -194,7 +194,7 @@
void acpi_create_gnvs(struct global_nvs_t *gnvs) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index e71c573..2bb908c 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -107,7 +107,7 @@ static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 8a65ccf..0ecccb9 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -40,7 +40,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
if (conf->speed_shift_enable) { @@ -67,7 +67,7 @@ { msr_t msr;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 086787d..a70b5a1 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -83,7 +83,7 @@ * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e31e47b..8819e7d 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -31,7 +31,7 @@ static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; @@ -69,7 +69,7 @@
struct device *dev; struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 28fc01d..6348d28 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -84,7 +84,7 @@
static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc();
rtc_init();
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index a70840b..c20da50 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -174,7 +174,7 @@ { DEVTREE_CONST struct soc_intel_icelake_config *config;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a4..5bf3421 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -79,7 +79,7 @@ const struct soc_intel_icelake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 8db2c3b..b7c37d4 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -76,7 +76,7 @@ { const struct soc_intel_icelake_config *config;
- config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a64fed4..cd654d7 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -93,7 +93,7 @@ "Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */ - config = config_of_path(LPC_DEV_FUNC); + config = config_of_soc();
/* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d67b502..de37341 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -172,7 +172,7 @@
static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc();
/* Set unknown wake source */ gnvs->pm1i = -1; @@ -232,7 +232,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc();
/* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); @@ -503,7 +503,7 @@ int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable;
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", @@ -674,7 +674,7 @@ /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 462285c2..55fedd3 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -237,7 +237,7 @@ uintptr_t vbt_data = (uintptr_t)vbt_get(); int i;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc();
mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28..5424c91 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val;
- config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -240,7 +240,7 @@
static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -260,7 +260,7 @@
static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -286,7 +286,7 @@
static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr;
@@ -562,7 +562,7 @@
int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc();
sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe0605..ab9297f 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -188,7 +188,7 @@ */ static void pm1_handle_wake_pin(void *unused) { - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc();
/* If WAKE# pin is enabled, bail out early. */ if (conf->deep_sx_config & DSX_EN_WAKE_PIN) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b03..329cea9 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -177,7 +177,7 @@ { DEVTREE_CONST struct soc_intel_skylake_config *config;
- config = config_of_path(PCH_DEVFN_PMC); + config = config_of_soc();
/* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a8bbfb6..f354af3 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -43,7 +43,7 @@ /* Program MCHBAR and DMIBAR */ systemagent_early_init();
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* Force a full memory train if RMT is enabled */ params->disable_saved_data = config->Rmt; @@ -57,7 +57,7 @@
/* Set the parameters for MemoryInit */
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
/* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index deda533..af89441 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -289,7 +289,7 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
- config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc();
soc_memory_init_params(m_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..bf0d506 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -29,7 +29,7 @@ const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL;
- config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); if (config->ignore_vtd) return;
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35656 )
Change subject: soc/intel: Replace config_of_path() with config_of_soc() ......................................................................
Patch Set 5: Code-Review+1
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Kyösti Mälkki (Code Review)
-
Marshall Dawson (Code Review)
-
Patrick Georgi (Code Review)