Change in coreboot[master]: soc/intel/skylake: add soc implementation for ETR address API

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36569 )

Change subject: soc/intel/skylake: add soc implementation for ETR address API
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Patch Set 4: Code-Review-1

(1 comment)

https://review.coreboot.org/c/coreboot/+/36569/4/src/soc/intel/skylake/pmuti... 
File src/soc/intel/skylake/pmutil.c:

https://review.coreboot.org/c/coreboot/+/36569/4/src/soc/intel/skylake/pmuti... 
PS4, Line 178: pcicfg(PCH_DEVFN_PMC << 12)->reg32[ETR / sizeof(uint32_t)];
             : }
That should not be exposed outside of pci_mmio_cfg.h. Why not use the regular pci ops?