Change in coreboot[master]: soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc
Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc ......................................................................
soc/intel/xeon_sp/cpx: update FSP to ww32 release and adapt soc
CPX-SP ww32 has a number of new features and bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the PCIe NIC device not working. ww32 release added two UDP parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to vt-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable vt-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. A separate PR will be submitted to enable it in coreboot.
There is a change in IIO UDS Hob.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44257/1
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 7093ec9..96949fd 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -57,5 +57,9 @@ /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ m_cfg->PchAdrEn = 0x02;
+ /* Make all IIO PCIe ports and port menus visible */ + m_cfg->PEXPHIDE = 0x0; + m_cfg->HidePEXPMenu = 0x0; + mainboard_memory_init_params(mupd); } diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 144db07..3517522 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -326,43 +326,45 @@ **/ UINT8 TorThresLoctoremEmpty;
-/** Offset 0x008D - TSC Sync in Sockets +/** Offset 0x008D - MBA BW Calibration + MBA BW Calibration setting + 0:Linear, 1:Biased, 2:Legacy, 3:Auto +**/ + UINT8 MbeBwCal; + +/** Offset 0x008E - TSC Sync in Sockets Enable or Disable TSC Sync in Sockets **/ UINT8 TscSyncEn;
-/** Offset 0x008E - HA A to S directory optimization +/** Offset 0x008F - HA A to S directory optimization Enable or Disable HA A to S directory optimization **/ UINT8 StaleAtoSOptEn;
-/** Offset 0x008F - LLC Deadline Allocation +/** Offset 0x0090 - LLC Deadline Allocation Enable or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc;
-/** Offset 0x0090 - Split Lock +/** Offset 0x0091 - Split Lock Enable or Disable Split Lock **/ UINT8 SplitLock;
-/** Offset 0x0091 - MMCFG Base Address +/** Offset 0x0092 - MMCFG Base Address Setup MMCFG Base Address 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto **/ UINT8 mmCfgBase;
-/** Offset 0x0092 - MMCFG Size +/** Offset 0x0093 - MMCFG Size Select MMCFG Size 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto **/ UINT8 mmCfgSize;
-/** Offset 0x0093 -**/ - UINT8 UnusedUpdSpace0; - /** Offset 0x0094 - MMIO High Base Address MMIO High Base Address, a hex number for Bit[51:32] **/ @@ -376,7 +378,7 @@
/** Offset 0x0099 **/ - UINT8 UnusedUpdSpace1; + UINT8 UnusedUpdSpace0;
/** Offset 0x009A - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space @@ -398,7 +400,7 @@
/** Offset 0x009E **/ - UINT8 UnusedUpdSpace2[2]; + UINT8 UnusedUpdSpace1[2];
/** Offset 0x00A0 - } TYPE:{Combo Enable or Disable @@ -466,39 +468,44 @@ **/ UINT8 VmxEnable;
-/** Offset 0x00BD - IIO ConfigIOU0 +/** Offset 0x00BD - Usage type for Processor X2apic Function + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 X2apic; + +/** Offset 0x00BE - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8];
-/** Offset 0x00C5 - IIO ConfigIOU1 +/** Offset 0x00C6 - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8];
-/** Offset 0x00CD - IIO ConfigIOU2 +/** Offset 0x00CE - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8];
-/** Offset 0x00D5 - IIO ConfigIOU3 +/** Offset 0x00D6 - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8];
-/** Offset 0x00DD - IIO ConfigIOU4 +/** Offset 0x00DE - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8];
-/** Offset 0x00E5 +/** Offset 0x00E6 **/ - UINT8 UnusedUpdSpace3[3]; + UINT8 UnusedUpdSpace2[2];
/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr @@ -616,58 +623,77 @@ **/ UINT8 VtdSupport;
-/** Offset 0x0105 - PchSirqMode +/** Offset 0x0105 - Usage type for IIO Pcie Port Hide + Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible +**/ + UINT8 PEXPHIDE; + +/** Offset 0x0106 - Usage type for IIO Pcie Port Menu Hide + Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +**/ + UINT8 HidePEXPMenu; + +/** Offset 0x0107 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode;
-/** Offset 0x0106 - PchAdrEn +/** Offset 0x0108 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn;
-/** Offset 0x0107 - } TYPE:{Combo +/** Offset 0x0109 - ThermalDeviceEnable + Enable or Disable ThermalDeviceEnable with PCI or ACPI mode +**/ + UINT8 ThermalDeviceEnable; + +/** Offset 0x010A - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap;
-/** Offset 0x0108 - PCH PCIE PLL Ssc +/** Offset 0x010B - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc;
-/** Offset 0x0109 - Usage type for PCH PCIE Root Port Index +/** Offset 0x010C - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20];
-/** Offset 0x011D - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0120 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20];
-/** Offset 0x0131 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x0134 - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20];
-/** Offset 0x0145 - SerialIoUartDebugEnable +/** Offset 0x0148 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x0146 - ISA Serial Base selection +/** Offset 0x0149 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x014A - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x0148 +/** Offset 0x014C **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -688,9 +714,9 @@ **/ FSPM_CONFIG FspmConfig;
-/** Offset 0x0158 +/** Offset 0x015C **/ - UINT8 UnusedUpdSpace4[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x015E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 8dcac42..a9465e1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -155,7 +155,6 @@ uint8_t PcieSegment; UINT64_STRUCT SegMmcfgBase; uint16_t stackPresentBitmap; - uint16_t CxlPresentBitmap; uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44257
to look at the new patch set (#2).
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UDP parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to vt-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable vt-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. A separate PR will be submitted to enable it in coreboot.
There is a change in IIO UDS Hob.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44257/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44257
to look at the new patch set (#3).
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UDP parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to vt-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable vt-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. A separate PR will be submitted to enable it in coreboot.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44257/3
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 3: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG@12 PS3, Line 12: UDP UPD
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG@14 PS3, Line 14: vt-d VT-d (in two places)
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44257
to look at the new patch set (#5).
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44257/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 5: Code-Review+2
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG@12 PS3, Line 12: UDP
UPD
Done
https://review.coreboot.org/c/coreboot/+/44257/3//COMMIT_MSG@14 PS3, Line 14: vt-d
VT-d (in two places)
Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... PS6, Line 329: /** Offset 0x008D - MBA BW Calibration : MBA BW Calibration setting : 0:Linear, 1:Biased, 2:Legacy, 3:Auto : **/ : UINT8 MbeBwCal; What's the default value for this option? I mean, if I'm not programming this in coreboot, what value will fsp set for this option? Auto?
Previously, the default value was marked in * .h files with UPD:
3rdparty/fsp/ApolloLakeFspBinPkg/Include/FspmUpd.h : 89 0x02:MMIO(Default).
Can you make appropriate notes here to avoid future confusion? And for other UPD options too...
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... PS6, Line 329: /** Offset 0x008D - MBA BW Calibration : MBA BW Calibration setting : 0:Linear, 1:Biased, 2:Legacy, 3:Auto : **/ : UINT8 MbeBwCal;
What's the default value for this option? […]
I will create an IPS ticket for this. The UPD header files are generated during FSP build process from *.dsc files. So it is not appropriate for us to hand update.
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/44257/6/src/vendorcode/intel/fsp/fs... PS6, Line 329: /** Offset 0x008D - MBA BW Calibration : MBA BW Calibration setting : 0:Linear, 1:Biased, 2:Legacy, 3:Auto : **/ : UINT8 MbeBwCal;
I will create an IPS ticket for this. […]
Ok, thanks.
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44257 )
Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc ......................................................................
vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt soc
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 3 files changed, 61 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 7093ec9..96949fd 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -57,5 +57,9 @@ /* Needed to avoid FSP-M reset. The default value of 0x01 is for MinPlatform */ m_cfg->PchAdrEn = 0x02;
+ /* Make all IIO PCIe ports and port menus visible */ + m_cfg->PEXPHIDE = 0x0; + m_cfg->HidePEXPMenu = 0x0; + mainboard_memory_init_params(mupd); } diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 144db07..3517522 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -326,43 +326,45 @@ **/ UINT8 TorThresLoctoremEmpty;
-/** Offset 0x008D - TSC Sync in Sockets +/** Offset 0x008D - MBA BW Calibration + MBA BW Calibration setting + 0:Linear, 1:Biased, 2:Legacy, 3:Auto +**/ + UINT8 MbeBwCal; + +/** Offset 0x008E - TSC Sync in Sockets Enable or Disable TSC Sync in Sockets **/ UINT8 TscSyncEn;
-/** Offset 0x008E - HA A to S directory optimization +/** Offset 0x008F - HA A to S directory optimization Enable or Disable HA A to S directory optimization **/ UINT8 StaleAtoSOptEn;
-/** Offset 0x008F - LLC Deadline Allocation +/** Offset 0x0090 - LLC Deadline Allocation Enable or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc;
-/** Offset 0x0090 - Split Lock +/** Offset 0x0091 - Split Lock Enable or Disable Split Lock **/ UINT8 SplitLock;
-/** Offset 0x0091 - MMCFG Base Address +/** Offset 0x0092 - MMCFG Base Address Setup MMCFG Base Address 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto **/ UINT8 mmCfgBase;
-/** Offset 0x0092 - MMCFG Size +/** Offset 0x0093 - MMCFG Size Select MMCFG Size 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto **/ UINT8 mmCfgSize;
-/** Offset 0x0093 -**/ - UINT8 UnusedUpdSpace0; - /** Offset 0x0094 - MMIO High Base Address MMIO High Base Address, a hex number for Bit[51:32] **/ @@ -376,7 +378,7 @@
/** Offset 0x0099 **/ - UINT8 UnusedUpdSpace1; + UINT8 UnusedUpdSpace0;
/** Offset 0x009A - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space @@ -398,7 +400,7 @@
/** Offset 0x009E **/ - UINT8 UnusedUpdSpace2[2]; + UINT8 UnusedUpdSpace1[2];
/** Offset 0x00A0 - } TYPE:{Combo Enable or Disable @@ -466,39 +468,44 @@ **/ UINT8 VmxEnable;
-/** Offset 0x00BD - IIO ConfigIOU0 +/** Offset 0x00BD - Usage type for Processor X2apic Function + Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +**/ + UINT8 X2apic; + +/** Offset 0x00BE - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8];
-/** Offset 0x00C5 - IIO ConfigIOU1 +/** Offset 0x00C6 - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8];
-/** Offset 0x00CD - IIO ConfigIOU2 +/** Offset 0x00CE - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8];
-/** Offset 0x00D5 - IIO ConfigIOU3 +/** Offset 0x00D6 - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8];
-/** Offset 0x00DD - IIO ConfigIOU4 +/** Offset 0x00DE - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8];
-/** Offset 0x00E5 +/** Offset 0x00E6 **/ - UINT8 UnusedUpdSpace3[3]; + UINT8 UnusedUpdSpace2[2];
/** Offset 0x00E8 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr @@ -616,58 +623,77 @@ **/ UINT8 VtdSupport;
-/** Offset 0x0105 - PchSirqMode +/** Offset 0x0105 - Usage type for IIO Pcie Port Hide + Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible +**/ + UINT8 PEXPHIDE; + +/** Offset 0x0106 - Usage type for IIO Pcie Port Menu Hide + Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +**/ + UINT8 HidePEXPMenu; + +/** Offset 0x0107 - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode;
-/** Offset 0x0106 - PchAdrEn +/** Offset 0x0108 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn;
-/** Offset 0x0107 - } TYPE:{Combo +/** Offset 0x0109 - ThermalDeviceEnable + Enable or Disable ThermalDeviceEnable with PCI or ACPI mode +**/ + UINT8 ThermalDeviceEnable; + +/** Offset 0x010A - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap;
-/** Offset 0x0108 - PCH PCIE PLL Ssc +/** Offset 0x010B - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc;
-/** Offset 0x0109 - Usage type for PCH PCIE Root Port Index +/** Offset 0x010C - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20];
-/** Offset 0x011D - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0120 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20];
-/** Offset 0x0131 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x0134 - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20];
-/** Offset 0x0145 - SerialIoUartDebugEnable +/** Offset 0x0148 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable;
-/** Offset 0x0146 - ISA Serial Base selection +/** Offset 0x0149 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x014A - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase;
-/** Offset 0x0148 +/** Offset 0x014C **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -688,9 +714,9 @@ **/ FSPM_CONFIG FspmConfig;
-/** Offset 0x0158 +/** Offset 0x015C **/ - UINT8 UnusedUpdSpace4[6]; + UINT8 UnusedUpdSpace4[2];
/** Offset 0x015E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 8dcac42..a9465e1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -155,7 +155,6 @@ uint8_t PcieSegment; UINT64_STRUCT SegMmcfgBase; uint16_t stackPresentBitmap; - uint16_t CxlPresentBitmap; uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha;
-
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