Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31209
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
src/soc/intel/common: Clear GPIO driver ownership when not requested
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested.
BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short keithshort@chromium.org --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 17 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31209/1
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 294218c..51e7b47 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -131,23 +131,30 @@ static void gpio_configure_owner(const struct pad_config *cfg, const struct pad_community *comm) { - uint16_t hostsw_reg; + uint32_t hostsw_own; + uint16_t hostsw_own_offset; int pin;
pin = relative_pad_in_comm(comm, cfg->pad);
- /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad - * needs GPIO driver ownership. - */ - if (!(cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)) - return; - /* Based on the gpio pin number configure the corresponding bit in * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. */ - hostsw_reg = comm->host_own_reg_0; - hostsw_reg += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); - pcr_or32(comm->port, hostsw_reg, gpio_bitmask_within_group(comm, pin)); + hostsw_own_offset = comm->host_own_reg_0; + hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); + + hostsw_own = pcr_read32(comm->port, hostsw_own_offset); + + /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. Set the bit if GPIO driver ownership + * requested, otherwise clear the bit. + */ + if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + hostsw_own |= gpio_bitmask_within_group(comm, pin); + else + hostsw_own &= ~gpio_bitmask_within_group(comm, pin); + + pcr_write32(comm->port, hostsw_own_offset, hostsw_own); }
static void gpi_enable_smi(const struct pad_config *cfg,
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... PS1, Line 144: hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); line over 80 characters
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 1: Code-Review+2
Hello Aaron Durbin, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31209
to look at the new patch set (#2).
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
src/soc/intel/common: Clear GPIO driver ownership when not requested
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested.
BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short keithshort@chromium.org --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 17 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31209/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31209/2/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31209/2/src/soc/intel/common/block/gpio/gpio... PS2, Line 144: hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); line over 80 characters
Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... PS1, Line 144: hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t));
line over 80 characters
Done
Hello Aaron Durbin, Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31209
to look at the new patch set (#3).
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
src/soc/intel/common: Clear GPIO driver ownership when not requested
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested.
BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short keithshort@chromium.org --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 18 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/31209/3
Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 3:
(1 comment)
My apologies for the multiple patches - had the wrong editor when trying to fix the line too long error.
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/#/c/31209/1/src/soc/intel/common/block/gpio/gpio... PS1, Line 144: hostsw_own_offset += gpio_group_index_scaled(comm, pin, sizeof(uint32_t));
Done
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31209 )
Change subject: src/soc/intel/common: Clear GPIO driver ownership when not requested ......................................................................
src/soc/intel/common: Clear GPIO driver ownership when not requested
The default state of the HOSTSW_OWN register in the PCH is zero, which configures GPIO pins for ACPI ownership. The board variabt GPIO tables can request specific pins to be configured for GPIO driver ownership. This change sets the HOSTSW_OWN ownership bit when requested and explicitly clears the ownership bit if not requested.
BUG=b:120884290 BRANCH=none TEST=Build coreboot on sarien. Verified UEFI to coreboot transition boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5 Signed-off-by: Keith Short keithshort@chromium.org Reviewed-on: https://review.coreboot.org/c/31209 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 18 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 294218c..6390315 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -131,23 +131,31 @@ static void gpio_configure_owner(const struct pad_config *cfg, const struct pad_community *comm) { - uint16_t hostsw_reg; + uint32_t hostsw_own; + uint16_t hostsw_own_offset; int pin;
pin = relative_pad_in_comm(comm, cfg->pad);
- /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad - * needs GPIO driver ownership. - */ - if (!(cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER)) - return; - /* Based on the gpio pin number configure the corresponding bit in * HOSTSW_OWN register. Value of 0x1 indicates GPIO Driver onwership. */ - hostsw_reg = comm->host_own_reg_0; - hostsw_reg += gpio_group_index_scaled(comm, pin, sizeof(uint32_t)); - pcr_or32(comm->port, hostsw_reg, gpio_bitmask_within_group(comm, pin)); + hostsw_own_offset = comm->host_own_reg_0; + hostsw_own_offset += gpio_group_index_scaled(comm, pin, + sizeof(uint32_t)); + + hostsw_own = pcr_read32(comm->port, hostsw_own_offset); + + /* The 4th bit in pad_config 1 (RO) is used to indicate if the pad + * needs GPIO driver ownership. Set the bit if GPIO driver ownership + * requested, otherwise clear the bit. + */ + if (cfg->pad_config[1] & PAD_CFG1_GPIO_DRIVER) + hostsw_own |= gpio_bitmask_within_group(comm, pin); + else + hostsw_own &= ~gpio_bitmask_within_group(comm, pin); + + pcr_write32(comm->port, hostsw_own_offset, hostsw_own); }
static void gpi_enable_smi(const struct pad_config *cfg,