Change in coreboot[master]: nb/intel/sandybridge: add and use more MCHBAR register defines
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
nb/intel/sandybridge: add and use more MCHBAR register defines
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 4 files changed, 30 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38010/1
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..0362330 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -101,9 +101,9 @@ u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; int i, refclk;
- addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0ba1678..5b388de 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -229,8 +229,8 @@ reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); - MCHBAR32(0x400 * channel + 0x4000) = reg; + printram("DBP [%x] = %x\n", TC_DBP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_DBP_C0 + 0x400 * channel) = reg;
// RAP reg = 0; @@ -241,8 +241,8 @@ reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); - MCHBAR32(0x400 * channel + 0x4004) = reg; + printram("RAP [%x] = %x\n", TC_RAP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg;
// OTHP addr = 0x400 * channel + 0x400c; @@ -271,10 +271,10 @@ reg = ((ctrl->tREFI & 0xffff) << 0) | ((ctrl->tRFC & 0x1ff) << 16) | (((val32 / 1024) & 0x7f) << 25); - printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); - MCHBAR32(0x400 * channel + 0x4298) = reg; + printram("REFI [%x] = %x\n", TC_RFTP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RFTP_C0 + 0x400 * channel) = reg;
- MCHBAR32_OR(0x400 * channel + 0x4294, 0xff); + MCHBAR32_OR(TC_RFP_C0 + 0x400 * channel, 0xff);
// SRFTP reg = 0; @@ -340,7 +340,7 @@ { int channel; FOR_ALL_CHANNELS { - MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel]; + MCHBAR32(MAD_DIMM_CH0 + channel * 4) = ctrl->mad_dimm[channel]; } }
@@ -364,14 +364,14 @@ reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x24; + MCHBAR32(MAD_CHNL) = 0x24; } else { reg = MCHBAR32(0x5014); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x21; + MCHBAR32(MAD_CHNL) = 0x21; } }
@@ -926,7 +926,7 @@
void program_timings(ramctr_timing * ctrl, int channel) { - u32 reg32, reg_4024, reg_c14, reg_c18, reg_4028; + u32 reg32, reg_4024, reg_c14, reg_c18, reg_io_latency; int lane; int slotrank, slot; int full_shift = 0; @@ -988,8 +988,8 @@ MCHBAR32(0xc14 + channel * 0x100) = reg_c14; MCHBAR32(0xc18 + channel * 0x100) = reg_c18;
- reg_4028 = MCHBAR32(0x4028 + 0x400 * channel); - reg_4028 &= 0xffff0000; + reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); + reg_io_latency &= 0xffff0000;
reg_4024 = 0;
@@ -1025,7 +1025,7 @@ post_timA_max_high - post_timA_min_high) shift_402x = -1;
- reg_4028 |= + reg_io_latency |= (ctrl->timings[channel][slotrank].val_4028 + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= @@ -1065,7 +1065,7 @@ } } MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; - MCHBAR32(0x4028 + 0x400 * channel) = reg_4028; + MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; }
static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) @@ -3169,7 +3169,7 @@ MCHBAR32_AND(0x58a8, ~0x1f);
FOR_ALL_CHANNELS - MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16);
MCHBAR32_OR(0x5030, 1); MCHBAR32_OR(0x5030, 0x80); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 84100e7..cab5588 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -149,9 +149,9 @@ u32 addr_decoder_common, addr_decode_ch[2]; int i;
- addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index a0fcb10..9ad3551 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,7 +127,15 @@ #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
+#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ +#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ +#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ +#define TC_RFP_C0 0x4294 /* Refresh Parameters */ +#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ #define PM_PDWN_Config 0x4cb0 +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ #define MC_BIOS_REQ 0x5e00 #define MC_BIOS_DATA 0x5e04 #define SSKPD 0x5d14 /* 16bit (scratchpad) */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1029: (ctrl->timings[channel][slotrank].val_4028 + shift_402x - Do you have a follow-up for .val_4028 or do you want to squash it here?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1: Code-Review+1
(16 comments)
Want MOAR register defines? :D
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 248: 0x400c TC_OTHP_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 362: 0x5014 MAD_ZR
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 988: 0xc14 GDCRCKPICODE_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 989: 0xc18 GDCRCKLOGICDELAY_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1067: 0x4024 SC_ROUNDT_LAT_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1073: 428c MCHBAR32(0x428C) == MCHBAR32(IOSAV_STATUS_C0)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3162: 0x4384 PM_CMD_PWR_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3167: 0x5880 MEM_TRML_ESTIMATION_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3168: 0x5888 MEM_TRML_THRESHOLDS_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3169: 0x58a8 MEM_TRML_CAMARILLO_INTERRUPT
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3174: 0x5030 MC_INIT_STATE_G
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3176: 0x5f18 BANDTIMERS
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3182: 0x4290 TC_ZQCAL_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 157: 0x5e04 MC_BIOS_DATA
it's already defined, btw :P
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config This should be all uppercase (maybe on another patchset): PM_PDWN_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 141: 0x5d14 I thought this was 0x5d10 ?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1029: (ctrl->timings[channel][slotrank].val_4028 + shift_402x -
Do you have a follow-up for . […]
missed that one; will do that in a follow-up patch
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1: Code-Review+2
(3 comments)
I'll add the missing registers myself, this patch is rather buried in the train
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3167: 0x5880
MEM_TRML_ESTIMATION_CONFIG
Done on CB:38015
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3168: 0x5888
MEM_TRML_THRESHOLDS_CONFIG
Done on CB:38015
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3169: 0x58a8
MEM_TRML_CAMARILLO_INTERRUPT
Done on CB:38015
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+2
(3 comments)
I'll add the missing registers myself, this patch is rather buried in the train
I'll add those in a follow-up patch; those don't need to be in this patch and I'm not too motivated to edit a patch in the middle of this patch train
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+2
(3 comments)
I'll add the missing registers myself, this patch is rather buried in the train
I'll add those in a follow-up patch; those don't need to be in this patch and I'm not too motivated to edit a patch in the middle of this patch train
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
(2 comments)
Patch Set 1:
Patch Set 1: Code-Review+2
(3 comments)
I'll add the missing registers myself, this patch is rather buried in the train
I'll add those in a follow-up patch; those don't need to be in this patch and I'm not too motivated to edit a patch in the middle of this patch train
That's what I meant. I'm taking care of it already.
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 157: 0x5e04
MC_BIOS_DATA […]
CB:38029
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config
This should be all uppercase (maybe on another patchset): PM_PDWN_CONFIG
CB:38028
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config
CB:38028
Done
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 141: 0x5d14
I thought this was 0x5d10 ?
yeah, i also wondered why 0x5d14 is used here. maybe to just use a part of the 64 bit register?! since I don't have hardware to test with me at the moment, I only did some cleanups that don't change the binary output
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1:
(12 comments)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 248: 0x400c
TC_OTHP_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 362: 0x5014
MAD_ZR
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 988: 0xc14
GDCRCKPICODE_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 989: 0xc18
GDCRCKLOGICDELAY_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1067: 0x4024
SC_ROUNDT_LAT_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1073: 428c
MCHBAR32(0x428C) == MCHBAR32(IOSAV_STATUS_C0)
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3162: 0x4384
PM_CMD_PWR_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3174: 0x5030
MC_INIT_STATE_G
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3176: 0x5f18
BANDTIMERS
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3182: 0x4290
TC_ZQCAL_C0
Ack
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config
CB:38028
Done
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 141: 0x5d14
I thought this was 0x5d10 ?
Will revise
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
nb/intel/sandybridge: add and use more MCHBAR register defines
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h 4 files changed, 30 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index c13ae37..0362330 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -101,9 +101,9 @@ u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; int i, refclk;
- addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0ba1678..5b388de 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -229,8 +229,8 @@ reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); - MCHBAR32(0x400 * channel + 0x4000) = reg; + printram("DBP [%x] = %x\n", TC_DBP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_DBP_C0 + 0x400 * channel) = reg;
// RAP reg = 0; @@ -241,8 +241,8 @@ reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); - MCHBAR32(0x400 * channel + 0x4004) = reg; + printram("RAP [%x] = %x\n", TC_RAP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RAP_C0 + 0x400 * channel) = reg;
// OTHP addr = 0x400 * channel + 0x400c; @@ -271,10 +271,10 @@ reg = ((ctrl->tREFI & 0xffff) << 0) | ((ctrl->tRFC & 0x1ff) << 16) | (((val32 / 1024) & 0x7f) << 25); - printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); - MCHBAR32(0x400 * channel + 0x4298) = reg; + printram("REFI [%x] = %x\n", TC_RFTP_C0 + 0x400 * channel, reg); + MCHBAR32(TC_RFTP_C0 + 0x400 * channel) = reg;
- MCHBAR32_OR(0x400 * channel + 0x4294, 0xff); + MCHBAR32_OR(TC_RFP_C0 + 0x400 * channel, 0xff);
// SRFTP reg = 0; @@ -340,7 +340,7 @@ { int channel; FOR_ALL_CHANNELS { - MCHBAR32(0x5004 + channel * 4) = ctrl->mad_dimm[channel]; + MCHBAR32(MAD_DIMM_CH0 + channel * 4) = ctrl->mad_dimm[channel]; } }
@@ -364,14 +364,14 @@ reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x24; + MCHBAR32(MAD_CHNL) = 0x24; } else { reg = MCHBAR32(0x5014); val = ch0size / 256; reg = (reg & ~0xff000000) | val << 24; reg = (reg & ~0xff0000) | (2 * val) << 16; MCHBAR32(0x5014) = reg; - MCHBAR32(0x5000) = 0x21; + MCHBAR32(MAD_CHNL) = 0x21; } }
@@ -926,7 +926,7 @@
void program_timings(ramctr_timing * ctrl, int channel) { - u32 reg32, reg_4024, reg_c14, reg_c18, reg_4028; + u32 reg32, reg_4024, reg_c14, reg_c18, reg_io_latency; int lane; int slotrank, slot; int full_shift = 0; @@ -988,8 +988,8 @@ MCHBAR32(0xc14 + channel * 0x100) = reg_c14; MCHBAR32(0xc18 + channel * 0x100) = reg_c18;
- reg_4028 = MCHBAR32(0x4028 + 0x400 * channel); - reg_4028 &= 0xffff0000; + reg_io_latency = MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel); + reg_io_latency &= 0xffff0000;
reg_4024 = 0;
@@ -1025,7 +1025,7 @@ post_timA_max_high - post_timA_min_high) shift_402x = -1;
- reg_4028 |= + reg_io_latency |= (ctrl->timings[channel][slotrank].val_4028 + shift_402x - post_timA_min_high) << (4 * slotrank); reg_4024 |= @@ -1065,7 +1065,7 @@ } } MCHBAR32(0x4024 + 0x400 * channel) = reg_4024; - MCHBAR32(0x4028 + 0x400 * channel) = reg_4028; + MCHBAR32(SC_IO_LATENCY_C0 + 0x400 * channel) = reg_io_latency; }
static void test_timA(ramctr_timing * ctrl, int channel, int slotrank) @@ -3169,7 +3169,7 @@ MCHBAR32_AND(0x58a8, ~0x1f);
FOR_ALL_CHANNELS - MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16); + MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16);
MCHBAR32_OR(0x5030, 1); MCHBAR32_OR(0x5030, 0x80); diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 84100e7..cab5588 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -149,9 +149,9 @@ u32 addr_decoder_common, addr_decode_ch[2]; int i;
- addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index a0fcb10..9ad3551 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -127,7 +127,15 @@ #define MCHBAR32_AND_OR(x, and, or) \ (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
+#define TC_DBP_C0 0x4000 /* Timing of DDR - bin parameters */ +#define TC_RAP_C0 0x4004 /* Timing of DDR - regular access parameters */ +#define SC_IO_LATENCY_C0 0x4028 /* IO Latency Configuration */ +#define TC_RFP_C0 0x4294 /* Refresh Parameters */ +#define TC_RFTP_C0 0x4298 /* Refresh Timing Parameters */ #define PM_PDWN_Config 0x4cb0 +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ #define MC_BIOS_REQ 0x5e00 #define MC_BIOS_DATA 0x5e04 #define SSKPD 0x5d14 /* 16bit (scratchpad) */
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