Want MOAR register defines? :D
Patch set 1:Code-Review +1
16 comments:
File src/northbridge/intel/sandybridge/raminit_common.c:
Patch Set #1, Line 248: 0x400c
TC_OTHP_C0
Patch Set #1, Line 362: 0x5014
MAD_ZR
Patch Set #1, Line 988: 0xc14
GDCRCKPICODE_C0
Patch Set #1, Line 989: 0xc18
GDCRCKLOGICDELAY_C0
Patch Set #1, Line 1067: 0x4024
SC_ROUNDT_LAT_C0
MCHBAR32(0x428C) == MCHBAR32(IOSAV_STATUS_C0)
Patch Set #1, Line 3162: 0x4384
PM_CMD_PWR_C0
Patch Set #1, Line 3167: 0x5880
MEM_TRML_ESTIMATION_CONFIG
Patch Set #1, Line 3168: 0x5888
MEM_TRML_THRESHOLDS_CONFIG
Patch Set #1, Line 3169: 0x58a8
MEM_TRML_CAMARILLO_INTERRUPT
Patch Set #1, Line 3174: 0x5030
MC_INIT_STATE_G
Patch Set #1, Line 3176: 0x5f18
BANDTIMERS
Patch Set #1, Line 3182: 0x4290
TC_ZQCAL_C0
File src/northbridge/intel/sandybridge/raminit_mrc.c:
Patch Set #1, Line 157: 0x5e04
MC_BIOS_DATA
it's already defined, btw :P
File src/northbridge/intel/sandybridge/sandybridge.h:
Patch Set #1, Line 135: PM_PDWN_Config
This should be all uppercase (maybe on another patchset): PM_PDWN_CONFIG
Patch Set #1, Line 141: 0x5d14
I thought this was 0x5d10 ?
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