Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63294 )

Change subject: mb/google/brya: Disable PCH USB2 phy power gating
......................................................................

mb/google/brya: Disable PCH USB2 phy power gating

The patch disables PCH USB2 Phy power gating.

BUG=b:221461379
TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla 
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63294/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index f2276d0..a110f98 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -22,6 +22,9 @@
    # Enable CNVi BT
    register "cnvi_bt_core" = "true"

+	# Disable PCH USB2 Phy power gating
+	register "usb2_phy_sus_pg_disable" = "1"
+
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
    register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2