[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

[Sean Rhodes (Code Review)]

Attention is currently required from: Dinesh Gehlot, Jeremy Compostella, Jérémy Compostella, Kapil Porwal, Martin L Roth, Nick Vaccaro, Ronak Kanabar, Subrata Banik.

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/81080?usp=email )

Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
......................................................................

Patch Set 9:

(1 comment)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/81080/comment/2b39b116_c6382946?usp... :
PS9, Line 842: 	/*
> Isn't a board design specific topic ? Should it be handled in src/mainboard/... […]

I guess a board could use any GPIO for it, but currently, coreboot leaves FSP using pins that can't ever work - surely the default should be changed to what Intel recommend?