Change in coreboot[master]: soc/intel/skylake: Drop unreferenced devicetree settings

[Angel Pons (Code Review)]

Hello  Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48571

to review the following change.

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

soc/intel/skylake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons 
---
M src/soc/intel/skylake/chip.h
1 file changed, 0 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48571/1

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 58d172f..bc37f1a 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -94,17 +94,6 @@
    int ignore_vtd;

/*
-	 * The following fields come from FspUpdVpd.h.
-	 * These are configuration values that are passed to FSP during
-	 * MemoryInit.
-	 */
-	u64 PlatformMemorySize;
-	u8 SmramMask;
-	u8 MrcFastBoot;
-	u32 TsegSize;
-	u16 MmioSize;
-
-	/*
     * DDR Frequency Limit
     * 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
     */
@@ -314,8 +303,6 @@
    u8 HeciTimeouts;
    u8 HsioMessaging;

-	/* Gfx related */
-	u8 IgdDvmt50PreAlloc;
    enum {
    	Display_iGFX,
    	Display_PEG,
@@ -334,7 +321,6 @@
     */
    u32 LogoPtr;
    u32 LogoSize;
-	u32 GraphicsConfigPtr;
    u8 RtcLock;
    /* GPIO IRQ Route  The valid values is 14 or 15*/
    u8 GpioIrqSelect;

[Angel Pons (Code Review)]

Hello  Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48571

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

soc/intel/skylake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons 
---
M src/soc/intel/skylake/chip.h
1 file changed, 1 insertion(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48571/2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
PS2, Line 510: FastPkgCRampDisable
/cb-build/coreboot-gerrit.0/default/GOOGLE_CAROLINE/mainboard/google/glados/static.c:167:3: error: 'const struct soc_intel_skylake_config' has no member named 'FastPkgCRampDisable'; did you mean 'FastPkgCRampDisableIa'?
  .FastPkgCRampDisable = 0,

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
PS2, Line 510: FastPkgCRampDisable
> /cb-build/coreboot-gerrit.0/default/GOOGLE_CAROLINE/mainboard/google/glados/static. […]

Oops, CB:48579

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 3: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 3: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/48571/2/src/soc/intel/skylake/chip.... 
PS2, Line 510: FastPkgCRampDisable
> Oops, CB:48579

Done

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
PS3, Line 311: ApertureSize
Not referenced on Skylake.

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
PS3, Line 398: PmConfigPciClockRun
Duplicates `lpc_enable_pci_clk_cntl()` in `soc/intel/common/block/lpc/lpc_lib.c` which is unconditionally called. Should I create a follow-up?

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 3: Code-Review+1

[Angel Pons (Code Review)]

Hello  Felix Singer, V Sowmya, build bot (Jenkins), Nico Huber, Furquan Shaikh, Benjamin Doron, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48571

to look at the new patch set (#4).

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

soc/intel/skylake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons 
---
M src/soc/intel/skylake/chip.h
1 file changed, 1 insertion(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48571/4

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
File src/soc/intel/skylake/chip.h:

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
PS3, Line 311: ApertureSize
> Not referenced on Skylake.

Gone.

https://review.coreboot.org/c/coreboot/+/48571/3/src/soc/intel/skylake/chip.... 
PS3, Line 398: PmConfigPciClockRun
> Duplicates `lpc_enable_pci_clk_cntl()` in `soc/intel/common/block/lpc/lpc_lib. […]

Yes, please. Marking this as resolved since this comment doesn't need to block this patch.

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 4: Code-Review+1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 4:

Hi, mind revisiting this change please?

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 4: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

Patch Set 4:

Thanks Subrata!

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48571 )

Change subject: soc/intel/skylake: Drop unreferenced devicetree settings
......................................................................

soc/intel/skylake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571
Reviewed-by: Benjamin Doron 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/chip.h
1 file changed, 1 insertion(+), 21 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Benjamin Doron: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 58d172f..7b9871c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -94,17 +94,6 @@
    int ignore_vtd;

/*
-	 * The following fields come from FspUpdVpd.h.
-	 * These are configuration values that are passed to FSP during
-	 * MemoryInit.
-	 */
-	u64 PlatformMemorySize;
-	u8 SmramMask;
-	u8 MrcFastBoot;
-	u32 TsegSize;
-	u16 MmioSize;
-
-	/*
     * DDR Frequency Limit
     * 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
     */
@@ -311,11 +300,7 @@
    u8 ScsEmmcHs400TxDataDll;

u8 PttSwitch;
-	u8 HeciTimeouts;
-	u8 HsioMessaging;

-	/* Gfx related */
-	u8 IgdDvmt50PreAlloc;
    enum {
    	Display_iGFX,
    	Display_PEG,
@@ -323,7 +308,6 @@
    	Display_Auto,
    	Display_Switchable,
    } PrimaryDisplay;
-	u8 ApertureSize;
    u8 SkipExtGfxScan;
    u8 ScanExtGfxForLegacyOpRom;

@@ -334,8 +318,7 @@
     */
    u32 LogoPtr;
    u32 LogoSize;
-	u32 GraphicsConfigPtr;
-	u8 RtcLock;
+
    /* GPIO IRQ Route  The valid values is 14 or 15*/
    u8 GpioIrqSelect;
    /* SCI IRQ Select  The valid values is 9, 10, 11 and 20 21, 22, 23*/
@@ -506,9 +489,6 @@
     * 0b - Enabled
     * 1b - Disabled
     */
-	/* FSP 1.1 */
-	u8 FastPkgCRampDisable;
-	/* FSP 2.0 */
    u8 FastPkgCRampDisableIa;
    u8 FastPkgCRampDisableGt;
    u8 FastPkgCRampDisableSa;