Angel Pons submitted this change.
soc/intel/skylake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I76aa2327d440394a9176c023bc95fb34e713741e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48571
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M src/soc/intel/skylake/chip.h
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 58d172f..7b9871c 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -94,17 +94,6 @@
int ignore_vtd;
/*
- * The following fields come from FspUpdVpd.h.
- * These are configuration values that are passed to FSP during
- * MemoryInit.
- */
- u64 PlatformMemorySize;
- u8 SmramMask;
- u8 MrcFastBoot;
- u32 TsegSize;
- u16 MmioSize;
-
- /*
* DDR Frequency Limit
* 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
*/
@@ -311,11 +300,7 @@
u8 ScsEmmcHs400TxDataDll;
u8 PttSwitch;
- u8 HeciTimeouts;
- u8 HsioMessaging;
- /* Gfx related */
- u8 IgdDvmt50PreAlloc;
enum {
Display_iGFX,
Display_PEG,
@@ -323,7 +308,6 @@
Display_Auto,
Display_Switchable,
} PrimaryDisplay;
- u8 ApertureSize;
u8 SkipExtGfxScan;
u8 ScanExtGfxForLegacyOpRom;
@@ -334,8 +318,7 @@
*/
u32 LogoPtr;
u32 LogoSize;
- u32 GraphicsConfigPtr;
- u8 RtcLock;
+
/* GPIO IRQ Route The valid values is 14 or 15*/
u8 GpioIrqSelect;
/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/
@@ -506,9 +489,6 @@
* 0b - Enabled
* 1b - Disabled
*/
- /* FSP 1.1 */
- u8 FastPkgCRampDisable;
- /* FSP 2.0 */
u8 FastPkgCRampDisableIa;
u8 FastPkgCRampDisableGt;
u8 FastPkgCRampDisableSa;
To view, visit change 48571. To unsubscribe, or for help writing mail filters, visit settings.