Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 7480174..0094db6 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -13,9 +13,9 @@
int pch_silicon_revision(void) { - static int pch_revision_id = -1; + static int pch_revision_id = 0;
- if (pch_revision_id < 0) + if (!pch_revision_id) pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
return pch_revision_id; @@ -23,9 +23,9 @@
int pch_silicon_type(void) { - static int pch_type = -1; + static int pch_type = 0;
- if (pch_type < 0) + if (!pch_type) pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return pch_type;
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49168
to look at the new patch set (#2).
Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/2
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49168?usp=email )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
Abandoned
Angel Pons has restored this change. ( https://review.coreboot.org/c/coreboot/+/49168?usp=email )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
Restored
Attention is currently required from: Angel Pons.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49168?usp=email )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
Patch Set 2: Code-Review+2
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49168?usp=email )
(
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: sb/intel/bd82x6x: Rework PCH ID cache ......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/49168 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Singer service+coreboot-gerrit@felixsinger.de --- M src/southbridge/intel/bd82x6x/common.c 1 file changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c index 7163d3e..63d2fb2 100644 --- a/src/southbridge/intel/bd82x6x/common.c +++ b/src/southbridge/intel/bd82x6x/common.c @@ -14,9 +14,9 @@
int pch_silicon_revision(void) { - static int pch_revision_id = -1; + static int pch_revision_id = 0;
- if (pch_revision_id < 0) + if (!pch_revision_id) pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
return pch_revision_id; @@ -24,9 +24,9 @@
int pch_silicon_type(void) { - static int pch_type = -1; + static int pch_type = 0;
- if (pch_type < 0) + if (!pch_type) pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return pch_type;
-
Angel Pons (Code Review) -
Felix Singer (Code Review)
-
Stefan Reinauer (Code Review)