Angel Pons uploaded patch set #2 to this change.

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sb/intel/bd82x6x: Rework PCH ID cache

Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.

Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons <>
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh:// refs/changes/68/49168/2

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Gerrit-Change-Number: 49168
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <>
Gerrit-Reviewer: Patrick Rudolph <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset