Change in coreboot[master]: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smbus_spd.c 4 files changed, 24 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/1
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index c3a4d41..f6cba68 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,6 +17,7 @@ #define _HUDSON_EARLY_SETUP_C_
#include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -74,11 +75,7 @@ pci_devfn_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 8eb36f4..a63f5e6 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> @@ -126,16 +127,10 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 34a3513..6e47e42 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,6 +18,7 @@
#include <assert.h> #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> @@ -36,18 +37,17 @@ { u8 byte;
- byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16))); + byte = aoac_read8(FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); - byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), + byte); + + aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); + iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ + iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ + iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ + iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */
udelay(2000); write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), @@ -107,11 +107,7 @@ pci_devfn_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); + pm_io_write8(0xec, pm_io_read8(0xec) | 1);
/* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3); @@ -236,8 +232,7 @@ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); + biosram_write8(nvram_pos, (dword >> (8 * i)) & 0xff); nvram_pos++; }
@@ -249,9 +244,8 @@ u32 data = *old_dword; int i; for (i = 0; i < size; i++) { - outb(nvram_pos, BIOSRAM_INDEX); data &= ~(0xff << (i * 8)); - data |= inb(BIOSRAM_DATA) << (i *8); + data |= biosram_read8(nvram_pos) << (i *8); nvram_pos++; } *old_dword = data; @@ -268,11 +262,11 @@ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + ctrl = misc_read32(FCH_MISC_REG40);
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ ctrl &= (u32)~(1<<2); - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); + misc_write32(FCH_MISC_REG40, ctrl); }
static uintptr_t hudson_spibase(void) diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index c49ccff..c046c28 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/pci_def.h> #include <device/device.h> @@ -127,16 +128,10 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_io_write8(0x2d, ioBase >> 8); + pm_io_write8(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi,cimx}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37400/1/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/1/src/southbridge/amd/pi/huds... PS1, Line 248: data |= biosram_read8(nvram_pos) << (i *8); need consistent spacing around '*' (ctx:WxV)
Hello Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#2).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smbus_spd.c 4 files changed, 24 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/2
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 2:
Wanted to put ACPIMMIO into CIMX's romcc bootblock southbridge initialization, but romcc seems to not like it.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 2:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 87: int s3_save_nvram_early(u32 dword, int size, int nvram_pos) Separate commit, remove as unused and prototypes in hudson.h too. It's really yet another BIOSRAM implementation.
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 101: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) as above
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 133: pm_io_write8(0x2c, ioBase | 1); pm_io_write16() ?
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 134: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz this is just outb() put perhaps swapped parameter order.
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 229: int s3_save_nvram_early(u32 dword, int size, int nvram_pos) remove
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 242: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) remove
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 134: pm_io_write8(0x2c, ioBase | 1); pm_io_write16() perhaps?
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 135: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz outb()
Kyösti Mälkki has uploaded a new patch set (#3) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/smbus_spd.c 4 files changed, 22 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 87: int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
Separate commit, remove as unused and prototypes in hudson.h too. […]
Done
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 101: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
as above
Done
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/early_setup.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 229: int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
remove
Done
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 242: int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
remove
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 4:
CB:37400 and CB:37401 are good cleanup, but can be postponed to be merged after apu1 and apu2 reach c-env-bootblock.
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#5).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 51 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37400/5/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/late.c:
https://review.coreboot.org/c/coreboot/+/37400/5/src/southbridge/amd/cimx/sb... PS5, Line 40: #include <southbridge/amd/common/amd_pci_util.h> missing <amdblocks/acpimmio.h>
Mike Banon has uploaded a new patch set (#6) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 52 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/6
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#7).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 52 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/7
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 7: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/37400/7/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/7/src/southbridge/amd/agesa/h... PS7, Line 133: pm_write8(0x2c, ioBase | 1); follow-up with pm_write16()
https://review.coreboot.org/c/coreboot/+/37400/7/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/7/src/southbridge/amd/pi/huds... PS7, Line 134: pm_write8(0x2c, ioBase | 1); follow-up pm_write16()
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 7:
(5 comments)
Marked some unresolved commits as followup work.
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 133: pm_io_write8(0x2c, ioBase | 1);
pm_io_write16() ?
Ack
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/agesa/h... PS2, Line 134: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
this is just outb() put perhaps swapped parameter order.
Ack
https://review.coreboot.org/c/coreboot/+/37400/5/src/southbridge/amd/cimx/sb... File src/southbridge/amd/cimx/sb800/late.c:
https://review.coreboot.org/c/coreboot/+/37400/5/src/southbridge/amd/cimx/sb... PS5, Line 40: #include <southbridge/amd/common/amd_pci_util.h>
missing <amdblocks/acpimmio. […]
Done
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... File src/southbridge/amd/pi/hudson/smbus_spd.c:
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 134: pm_io_write8(0x2c, ioBase | 1);
pm_io_write16() perhaps?
Ack
https://review.coreboot.org/c/coreboot/+/37400/2/src/southbridge/amd/pi/huds... PS2, Line 135: __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
outb()
Ack
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#8).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 168 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/8
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 8:
Also got rid of __outbyte, __inbyte and __rdtsc
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 8:
Patch Set 8:
Also got rid of __outbyte, __inbyte and __rdtsc
Hmmm.. can you put this back to #7 and make those separate ones.
FYI: That SMBUS might go away completely. From what I remember SMBUS host controller specification was not Intel proprietary and AMD implementation is compatible with the more complete one under southbridge/intel/common/smbus.
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#9).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 52 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/9
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#10).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 50 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/10
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37400
to look at the new patch set (#11).
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 50 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37400/11
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 11:
Patch Set 8:
Patch Set 8:
Also got rid of __outbyte, __inbyte and __rdtsc
Hmmm.. can you put this back to #7 and make those separate ones.
FYI: That SMBUS might go away completely. From what I remember SMBUS host controller specification was not Intel proprietary and AMD implementation is compatible with the more complete one under southbridge/intel/common/smbus.
I will look closer at it then
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
Patch Set 11: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37400 )
Change subject: sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible ......................................................................
sb/amd/{agesa,pi}: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ic3d5abc8f3b235ea61f66950ada8aff1dc48f8c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37400 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/southbridge/amd/agesa/hudson/early_setup.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/cimx/sb800/bootblock.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smbus_spd.c 9 files changed, 50 insertions(+), 63 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 639a5e8..090a852 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,6 +17,7 @@ #define _HUDSON_EARLY_SETUP_C_
#include <stdint.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> #include <console/console.h> #include <amdblocks/acpimmio.h> diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 1d63c1e..934d1e9 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -14,6 +14,7 @@ */
#include "imc.h" +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <Porting.h> #include <AGESA.h> @@ -22,24 +23,22 @@ #include <Proc/Fch/Common/FchCommonCfg.h> #include <Proc/Fch/FchPlatform.h>
-#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - void imc_reg_init(void) { /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff); + pm2_write8(0, 0x06); + pm2_write8(1, 0x06); + pm2_write8(2, 0xf7); + pm2_write8(3, 0xff); + pm2_write8(4, 0xff);
#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff); - write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff); + pm2_write8(0x10, 0x06); + pm2_write8(0x11, 0x06); + pm2_write8(0x12, 0xf7); + pm2_write8(0x13, 0xff); + pm2_write8(0x14, 0xff); #endif
#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index 8eb36f4..9ddae38 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> @@ -126,16 +127,9 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_write16(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 5decebf..6e0b544 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -83,7 +83,6 @@ static void enable_clocks(void) { u32 reg32; - volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program SB800 MiscClkCntrl register to configure clock output on the // 14M_25M_48M_OSC ball usually used for the Super-I/O. @@ -91,12 +90,12 @@ // which is the SB800's power up default. We could switch back to 14 // in the mainboard's romstage.c, but then the clock frequency would // change twice. - reg32 = *acpi_mmio; + reg32 = misc_read32(0x40); reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) #if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK) reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz #endif - *acpi_mmio = reg32; + misc_write32(0x40, reg32); }
void bootblock_early_southbridge_init(void) diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 4882957..2ee4d40 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -14,6 +14,7 @@ */
#include <stdint.h> +#include <amdblocks/acpimmio.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ @@ -41,9 +42,7 @@ */ void sb800_clk_output_48Mhz(void) { - /* AcpiMMioDecodeEn */ - RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ - *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ + misc_write32(0x40, misc_read32(0x40) & (~5)); + misc_write32(0x40, misc_read32(0x40) | 2); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 4233a6f..d6003be 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */
- +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> /* device_operations */ @@ -400,9 +400,9 @@ * to function as GPIO {GPIO 35:0}. */ if (!sb_chip->disconnect_pcib && dev->enabled) - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); + pm_write8(0xea, pm_read8(0xea) & 0xfe); else - RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0); + pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1); break;
case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 191a96c..fe75115 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,6 +18,7 @@
#include <assert.h> #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> @@ -36,18 +37,17 @@ { u8 byte;
- byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16))); + byte = aoac_read8(FCH_AOAC_REG56 + + CONFIG_UART_FOR_CONSOLE * sizeof(u16))); byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + - CONFIG_UART_FOR_CONSOLE * sizeof(u16)), byte); - byte = read8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62)); - byte |= 1 << 3; - write8((void *)(ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62), byte); - write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0); - write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0); - write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0); - write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0); + aoac_write8(FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * sizeof(u16)), + byte); + + aoac_write8(FCH_AOAC_REG62, aoac_read8(FCH_AOAC_REG62) | (1 << 3)); + iomux_write8(0x89, 0); /* UART0_RTS_L_EGPIO137 */ + iomux_write8(0x8a, 0); /* UART0_TXD_EGPIO138 */ + iomux_write8(0x8e, 0); /* UART1_RTS_L_EGPIO142 */ + iomux_write8(0x8f, 0); /* UART1_TXD_EGPIO143 */
udelay(2000); write8((void *)(0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88), @@ -229,11 +229,11 @@ * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); + ctrl = misc_read32(FCH_MISC_REG40);
/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ ctrl &= (u32)~(1<<2); - write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); + misc_write32(FCH_MISC_REG40, ctrl); }
static uintptr_t hudson_spibase(void) diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 6a01a76..3c6054d 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -16,6 +16,7 @@ #define __SIMPLE_DEVICE__
#include "imc.h" +#include <amdblocks/acpimmio.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/device.h> @@ -26,24 +27,24 @@ #include <Proc/Fch/Fch.h> #include <Proc/Fch/FchPlatform.h>
-#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) - void imc_reg_init(void) { u8 reg8; /* Init Power Management Block 2 (PM2) Registers. * Check BKDG for AMD Family 16h for details. */ - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x00), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x01), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x02), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x03), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x04), 0xff); + /* Init Power Management Block 2 (PM2) Registers. + * Check BKDG for AMD Family 16h for details. */ + pm2_write8(0, 0x06); + pm2_write8(1, 0x06); + pm2_write8(2, 0xf7); + pm2_write8(3, 0xff); + pm2_write8(4, 0xff);
- write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x10), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x11), 0x06); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x12), 0xf7); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x13), 0xff); - write8((VACPI_MMIO_VBASE + PMIO2_BASE + 0x14), 0xff); + pm2_write8(0x10, 0x06); + pm2_write8(0x11, 0x06); + pm2_write8(0x12, 0xf7); + pm2_write8(0x13, 0xff); + pm2_write8(0x14, 0xff);
reg8 = pci_read_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4); reg8 &= 0x8F; diff --git a/src/southbridge/amd/pi/hudson/smbus_spd.c b/src/southbridge/amd/pi/hudson/smbus_spd.c index c49ccff..8523db5 100644 --- a/src/southbridge/amd/pi/hudson/smbus_spd.c +++ b/src/southbridge/amd/pi/hudson/smbus_spd.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/pci_def.h> #include <device/device.h> @@ -127,16 +128,9 @@ return 0; }
-static void writePmReg (int reg, int data) -{ - __outbyte (0xCD6, reg); - __outbyte (0xCD7, data); -} - static void setupFch (int ioBase) { - writePmReg (0x2D, ioBase >> 8); - writePmReg (0x2C, ioBase | 1); + pm_write16(0x2c, ioBase | 1); __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz }
-
build bot (Jenkins) (Code Review) -
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Mike Banon (Code Review)