Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=none
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb 3 files changed, 59 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index a658b2a..8b1eb09 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,7 @@ select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_INTEL_DPTF
config BOARD_GOOGLE_HATCH_COMMON def_bool n diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a5aa702..2a0bb15 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -205,6 +205,64 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Puff boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(85, 90), + TEMP_PCT(80, 69), + TEMP_PCT(75, 56), + TEMP_PCT(70, 46), + TEMP_PCT(65, 36),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 64W, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 60000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44905
to look at the new patch set (#2).
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=none
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 14 files changed, 293 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/2
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
This change is ready for review.
Andrew McRae has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 270: # Default DPTF Policy for all Puff boards if not overridden Is this comment still accurate? Maybe 'DPTF Policy for duffy'
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 276: device pci 04.0 on So I wonder whether faffy has the same policy as the others. I do see that it had a separate config from the others. I don't know about these configs as to whether the old config was just a placeholder for faffy.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8: Code-Review-1
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8: -Code-Review
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 270: # Default DPTF Policy for all Puff boards if not overridden
Is this comment still accurate? […]
We could remove it however I left it as the almost all boards shared the same ASL before and so the comment made sense to keep.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 276: device pci 04.0 on
So I wonder whether faffy has the same policy as the others. […]
Faffy is fanless so the policy doesn't include fan configuration. The old ASL should even be doing `define DPTF_ENABLE_FAN_CONTROL`
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
(7 comments)
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 270: # Default DPTF Policy for all Puff boards if not overridden
Is this comment still accurate? […]
Let's remove it; it was more meaningful when it was in a baseboard devicetree.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 274: 90 The first values should be 90, 85, 80, 75, 70, 65. The second values should be 95, 85, 75, 65, 55, 45 - or possibly 85, ..., 45, ?, since the 95s are actually used as the weight in the source ASL.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 280: .thresholds={TEMP_PCT(50, 90), The second values should be 95, 85, ..., 45. This time, there's one fewer temperature in the source ASL so it doesn't fit in a different way.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 288: CHARGER CPU
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 298: 3000 15000
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 304: 15000 25000
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 305: 60000 64000
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
(6 comments)
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 279: ## Active Policy Remove?
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 289: register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 5000)"
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 292: register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 297: 3000 10000
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 303: 15000 25000
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 304: 60000 51000
Hello Sam McNally, build bot (Jenkins), David Wu, Tim Wawrzynczak, Andrew McRae,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44905
to look at the new patch set (#9).
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/overridetree.cb D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 15 files changed, 364 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/9
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 8:
(13 comments)
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 270: # Default DPTF Policy for all Puff boards if not overridden
Let's remove it; it was more meaningful when it was in a baseboard devicetree.
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 274: 90
The first values should be 90, 85, 80, 75, 70, 65. […]
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 280: .thresholds={TEMP_PCT(50, 90),
The second values should be 95, 85, ..., 45. […]
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 288: CHARGER
CPU
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 298: 3000
15000
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 304: 15000
25000
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 305: 60000
64000
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 279: ## Active Policy
Remove?
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 289:
register "policies. […]
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 292:
register "policies. […]
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 297: 3000
10000
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 303: 15000
25000
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 304: 60000
51000
Done
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44905/9/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/9/src/mainboard/google/hatch/... PS9, Line 279: 90 The first number in each pair should have remained the same: 50, 47, 45, 42, 39.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 289:
Done
In addition, not replacing. It was policies.passive[1] for a reason.
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 292:
Done
Ditto.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44905/9/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/9/src/mainboard/google/hatch/... PS9, Line 279: 90
The first number in each pair should have remained the same: 50, 47, 45, 42, 39.
Done
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 289:
In addition, not replacing. It was policies.passive[1] for a reason.
I misread
https://review.coreboot.org/c/coreboot/+/44905/8/src/mainboard/google/hatch/... PS8, Line 292:
Ditto.
Done
Hello Sam McNally, build bot (Jenkins), David Wu, Tim Wawrzynczak, Andrew McRae,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44905
to look at the new patch set (#10).
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/overridetree.cb D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 15 files changed, 366 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/10
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44905/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/10/src/mainboard/google/hatch... PS10, Line 209: # Default DPTF Policy for all Puff boards if not overridden Probably remove this too.
Hello Sam McNally, build bot (Jenkins), David Wu, Tim Wawrzynczak, Andrew McRae,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44905
to look at the new patch set (#11).
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/overridetree.cb D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 15 files changed, 365 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/11
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44905/10/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/10/src/mainboard/google/hatch... PS10, Line 209: # Default DPTF Policy for all Puff boards if not overridden
Probably remove this too.
Done
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 11: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 274: .thresholds={TEMP_PCT(90, 85), : TEMP_PCT(85, 75), : TEMP_PCT(75, 65), : TEMP_PCT(65, 55), : TEMP_PCT(55, 45),}}" This is slightly different than dptf.asl, should be: 90, 85 85, 75, 80, 65 75, 55 70, 45
note that there's an extra _AC5 in the dptf.asl which has a corresponding fan speed of 0
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 295: # 10-15W PL1 in 200mW increments, avg over 28-32s interval : # PL2 is fixed at 64W, avg over 28-32s interval These comments are not accurate; PL1 is fixed at 15W here, and PL2 can range from 25-64W
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 12:
(9 comments)
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 288: is fixed at 64W ranges from 25 to 51W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/kaisa/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 295: 10-15W PL1 PL1 fixed at 15W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 296: PL2 is fixed at 64W PL2 ranges from 25 to 64W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/noibat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 221: 10-15W PL1 PL1 fixed at 15W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 222: PL2 is fixed at 64W PL2 ranges from 25 to 64W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 233: 10-15W PL1 in 200mW increments PL1 fixed at 15W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 234: PL2 is fixed at 64W PL2 ranges from 25 to 64W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/wyvern/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 228: 10-15W PL1 in 200mW increments PL1 fixed at 15W
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 229: PL2 is fixed at 64W PL2 ranges from 25 to 64W
Hello Sam McNally, build bot (Jenkins), David Wu, Tim Wawrzynczak, Andrew McRae,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44905
to look at the new patch set (#13).
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/overridetree.cb D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 15 files changed, 365 insertions(+), 198 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/44905/13
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 12:
(11 comments)
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 274: .thresholds={TEMP_PCT(90, 85), : TEMP_PCT(85, 75), : TEMP_PCT(75, 65), : TEMP_PCT(65, 55), : TEMP_PCT(55, 45),}}"
This is slightly different than dptf.asl, should be: […]
Fixed. Thank you.
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 295: # 10-15W PL1 in 200mW increments, avg over 28-32s interval : # PL2 is fixed at 64W, avg over 28-32s interval
These comments are not accurate; PL1 is fixed at 15W here, and PL2 can range from 25-64W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/faffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 288: is fixed at 64W
ranges from 25 to 51W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/kaisa/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 295: 10-15W PL1
PL1 fixed at 15W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 296: PL2 is fixed at 64W
PL2 ranges from 25 to 64W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/noibat/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 221: 10-15W PL1
PL1 fixed at 15W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 222: PL2 is fixed at 64W
PL2 ranges from 25 to 64W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/puff/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 233: 10-15W PL1 in 200mW increments
PL1 fixed at 15W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 234: PL2 is fixed at 64W
PL2 ranges from 25 to 64W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... File src/mainboard/google/hatch/variants/wyvern/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 228: 10-15W PL1 in 200mW increments
PL1 fixed at 15W
Done
https://review.coreboot.org/c/coreboot/+/44905/12/src/mainboard/google/hatch... PS12, Line 229: PL2 is fixed at 64W
PL2 ranges from 25 to 64W
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 13: Code-Review+2
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 13: Code-Review+2
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
Patch Set 13: Code-Review+2
Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44905 )
Change subject: mb/google/puff: Convert ASL file to new DPTF dt impl ......................................................................
mb/google/puff: Convert ASL file to new DPTF dt impl
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly.
BUG=b:158986928 BRANCH=puff TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b Signed-off-by: Edward O'Callaghan quasisec@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Sam McNally sammc@google.com Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/dsdt.asl D src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl D src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/duffy/overridetree.cb D src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/faffy/overridetree.cb D src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kaisa/overridetree.cb D src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/noibat/overridetree.cb D src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/puff/overridetree.cb D src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/wyvern/overridetree.cb 15 files changed, 365 insertions(+), 198 deletions(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Sam McNally: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index a658b2a..ee9210d 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -12,6 +12,8 @@ select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD select SOC_INTEL_CSE_LITE_SKU + select DRIVERS_INTEL_DPTF + select DPTF_USE_EISA_HID
config BOARD_GOOGLE_HATCH_COMMON def_bool n @@ -38,6 +40,7 @@ select MAINBOARD_HAS_TPM2 select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE select SOC_INTEL_COMETLAKE + select SOC_INTEL_COMMON_BLOCK_DTT
if BOARD_GOOGLE_HATCH_COMMON
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index ffb7cfe..d43a499 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -48,6 +48,7 @@ #include <ec/google/chromeec/acpi/ec.asl> }
+#if CONFIG(BOARD_GOOGLE_BASEBOARD_HATCH) /* Dynamic Platform Thermal Framework */ Scope (_SB) { @@ -56,4 +57,5 @@ /* Include common dptf ASL files */ #include <soc/intel/common/acpi/dptf/dptf.asl> } +#endif } diff --git a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl b/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl deleted file mode 100644 index e0df9ba..0000000 --- a/src/mainboard/google/hatch/variants/baseboard/include/puff/acpi/dptf.asl +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 93 -#define DPTF_CPU_CRITICAL 100 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 85 -#define DPTF_CPU_ACTIVE_AC2 80 -#define DPTF_CPU_ACTIVE_AC3 75 -#define DPTF_CPU_ACTIVE_AC4 70 -#define DPTF_CPU_ACTIVE_AC5 65 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 75 -#define DPTF_TSR0_ACTIVE_AC0 50 -#define DPTF_TSR0_ACTIVE_AC1 47 -#define DPTF_TSR0_ACTIVE_AC2 45 -#define DPTF_TSR0_ACTIVE_AC3 42 -#define DPTF_TSR0_ACTIVE_AC4 39 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - _SB.DPTF.TFN1, _SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - _SB.DPTF.TFN1, _SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 15000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 64000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/duffy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb index a4fa09d..72f9516 100644 --- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb @@ -267,6 +267,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl deleted file mode 100644 index 40bc664..0000000 --- a/src/mainboard/google/hatch/variants/faffy/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define DPTF_CPU_PASSIVE 90 -#define DPTF_CPU_CRITICAL 100 - -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 60 -#define DPTF_TSR0_CRITICAL 85 - -#define DPTF_ENABLE_CHARGER -#define DPTF_ENABLE_FAN_CONTROL - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ - Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ - Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ -}) - -/* DFPS: Fan Performance States */ -Name (DFPS, Package () { - 0, // Revision - /* - * TODO : Need to update this Table after characterization. - * These are initial reference values. - */ - /* Control, Trip Point, Speed, NoiseLevel, Power */ - Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, - Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, - Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, - Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, - Package () {50, 0xFFFFFFFF, 3838, 90, 900}, - Package () {40, 0xFFFFFFFF, 2904, 55, 550}, - Package () {30, 0xFFFFFFFF, 2337, 30, 300}, - Package () {20, 0xFFFFFFFF, 1608, 15, 150}, - Package () {10, 0xFFFFFFFF, 800, 10, 100}, - Package () {0, 0xFFFFFFFF, 0, 0, 50} -}) - -Name (DART, Package () { - /* Fan effect on CPU */ - 0, // Revision - Package () { - /* - * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, - * AC7, AC8, AC9 - */ - _SB.DPTF.TFN1, _SB.PCI0.TCPU, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - }, - Package () { - _SB.DPTF.TFN1, _SB.DPTF.TSR0, 95, 85, 75, 65, 55, 45, 0, 0, - 0, 0, 0 - } -}) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.TCPU, _SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, - - /* CPU Throttle Effect on Ambient (TSR0) */ - Package () { _SB.PCI0.TCPU, _SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 10000, /* PowerLimitMinimum */ - 15000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 25000, /* PowerLimitMinimum */ - 51000, /* PowerLimitMaximum */ - 28000, /* TimeWindowMinimum */ - 32000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/hatch/variants/faffy/overridetree.cb index 61c7f0f..a5c8eff 100644 --- a/src/mainboard/google/hatch/variants/faffy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/faffy/overridetree.cb @@ -273,6 +273,41 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 60, 5000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + + ## Power Limits Control + # 10-15W PL1 in 200mW increments, avg over 28-32s interval + # 25-51W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 10000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/kaisa/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb index c6aef05..5fc9c08 100644 --- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb @@ -267,6 +267,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/noibat/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/hatch/variants/noibat/overridetree.cb index c73798a..de49462 100644 --- a/src/mainboard/google/hatch/variants/noibat/overridetree.cb +++ b/src/mainboard/google/hatch/variants/noibat/overridetree.cb @@ -193,6 +193,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/puff/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index a5aa702..fcbce27 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -205,6 +205,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl deleted file mode 100644 index 6694063..0000000 --- a/src/mainboard/google/hatch/variants/wyvern/include/variant/acpi/dptf.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <puff/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb index 3d5da00..24757b6 100644 --- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb +++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb @@ -200,6 +200,71 @@ register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(90, 85), + TEMP_PCT(85, 75), + TEMP_PCT(80, 65), + TEMP_PCT(75, 55), + TEMP_PCT(70, 45),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(50, 85), + TEMP_PCT(47, 75), + TEMP_PCT(45, 65), + TEMP_PCT(42, 55), + TEMP_PCT(39, 45),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + + ## Power Limits Control + # PL1 is fixed at 15W, avg over 28-32s interval + # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 25000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x1903 device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on
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Edward O'Callaghan (Code Review)
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