Change in coreboot[master]: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49052 )
Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ......................................................................
soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892 TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/49052/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ed34897..295f789 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -159,6 +159,9 @@ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else params->Usb2OverCurrentPin[i] = 0xff; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; }
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 69b5ca8..5dea4bf 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -31,6 +31,7 @@ uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; };
/* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ }
struct usb3_port_config {
Attention is currently required from: John Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49052 )
Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2: Thanks for the great commit message!
Attention is currently required from: John Zhao. Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49052 )
Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ......................................................................
Patch Set 2: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49052 )
Change subject: soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports ......................................................................
soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892 TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Chiranjeevi Rapolu chiranjeevi.rapolu@intel.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/include/soc/usb.h 2 files changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Chiranjeevi Rapolu: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index ed34897..295f789 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -159,6 +159,9 @@ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else params->Usb2OverCurrentPin[i] = 0xff; + + if (config->usb2_ports[i].type_c) + params->PortResetMessageEnable[i] = 1; }
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { diff --git a/src/soc/intel/tigerlake/include/soc/usb.h b/src/soc/intel/tigerlake/include/soc/usb.h index 69b5ca8..5dea4bf 100644 --- a/src/soc/intel/tigerlake/include/soc/usb.h +++ b/src/soc/intel/tigerlake/include/soc/usb.h @@ -31,6 +31,7 @@ uint8_t tx_emp_enable; uint8_t pre_emp_bias; uint8_t pre_emp_bit; + uint8_t type_c; };
/* USB Overcurrent pins definition */ @@ -112,6 +113,7 @@ .tx_emp_enable = USB2_PRE_EMP_ON, \ .pre_emp_bias = USB2_BIAS_56P3MV, \ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .type_c = 1, \ }
struct usb3_port_config {
-
Chiranjeevi Rapolu (Code Review) -
John Zhao (Code Review)
-
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)