Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 37 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/1
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4ebfa9d..fe2036f1f 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000..5dcf386 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 47a7d39..7e35239 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -15,73 +15,20 @@
#include <stdint.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pnp.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> -#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include <Fch/Fch.h>
#include "gpio_ftns.h"
-#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void);
void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data;
- /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - post_code(0x30); early_lpc_init();
- hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); if (val & (1 << 30)) {
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 7:
This change is ready for review.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36915/7//COMMIT_MSG@8 PS7, Line 8: Please elaborate on the code changes, and maybe comment on user visible changes like different timestamps.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig File src/cpu/amd/pi/Kconfig:
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig@54 PS7, Line 54: config PI_AGESA_CAR_HEAP_BASE : hex : default 0x10000000 : : config PI_AGESA_HEAP_SIZE : hex : default 0x30000 Is this related to this change?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig File src/cpu/amd/pi/Kconfig:
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig@54 PS7, Line 54: config PI_AGESA_CAR_HEAP_BASE : hex : default 0x10000000 : : config PI_AGESA_HEAP_SIZE : hex : default 0x30000
Is this related to this change?
Mistake during the rebase
Hello Piotr Król, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#8).
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 39 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/8
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig File src/cpu/amd/pi/Kconfig:
https://review.coreboot.org/c/coreboot/+/36915/7/src/cpu/amd/pi/Kconfig@54 PS7, Line 54: config PI_AGESA_CAR_HEAP_BASE : hex : default 0x10000000 : : config PI_AGESA_HEAP_SIZE : hex : default 0x30000
Mistake during the rebase
Done
Hello Piotr Król, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#10).
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 39 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/10
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 12: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/15/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/15/src/mainboard/pcengines/ap... PS15, Line 41: pm_io_write8(0xea, 1); We can do this tree-wide, regardless of C_ENV_BB, even for the disabled boards.
Hello Piotr Król, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#17).
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Kconfig.name M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 5 files changed, 46 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/17
Hello Piotr Król, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#20).
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Kconfig.name M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 5 files changed, 46 insertions(+), 67 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/20
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/15/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/15/src/mainboard/pcengines/ap... PS15, Line 41: pm_io_write8(0xea, 1);
We can do this tree-wide, regardless of C_ENV_BB, even for the disabled boards.
Tree-wide patches prepared.
Kyösti Mälkki has uploaded a new patch set (#24) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 39 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/24
Hello Kyösti Mälkki, Piotr Król, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#25).
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
mb/pcengines/apu2: move to C bootblock
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 39 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/25
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36915/7//COMMIT_MSG@8 PS7, Line 8:
Please elaborate on the code changes, and maybe comment on user visible changes like different times […]
Done
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: mb/pcengines/apu2: move to C bootblock ......................................................................
Patch Set 28:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36915/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36915/27//COMMIT_MSG@7 PS27, Line 7: mb/pcengines/apu2: move to C bootblock pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Just to be consistent with previous BINARYPI_LEGACY_WRAPPER titles.
https://review.coreboot.org/c/coreboot/+/36915/28/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/28/src/mainboard/pcengines/ap... PS28, Line 41: pm_io_write8(0xea, 1); pm_write8() now that ACPIMMIO is enabled in bootblock already?
Is there still PCI-PCI bridge 0:14.4 (?), I see this comment has origins in fam16kb.
Hello Kyösti Mälkki, Piotr Król, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#29).
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 39 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/29
Hello Kyösti Mälkki, Piotr Król, Arthur Heymans, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36915
to look at the new patch set (#30).
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 40 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/30
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 30:
(2 comments)
https://review.coreboot.org/c/coreboot/+/36915/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36915/27//COMMIT_MSG@7 PS27, Line 7: mb/pcengines/apu2: move to C bootblock
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK […]
Done
https://review.coreboot.org/c/coreboot/+/36915/28/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/28/src/mainboard/pcengines/ap... PS28, Line 41: pm_io_write8(0xea, 1);
pm_write8() now that ACPIMMIO is enabled in bootblock already? […]
No PCI-PCI bridge in BKDG or any other bit description than GenIntDIsable for GPIO32 and 33 in the PMxEA.
Kyösti Mälkki has uploaded a new patch set (#31) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 40 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/36915/31
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); We lost this in hudson/agesa|pi/early_setup.c ?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
We lost this in hudson/agesa|pi/early_setup. […]
Not exactly. LPC decode for SuperIO ports was never there actually. AGESA enables these decodes at some point, but for sure I couldn't configure UARTB on NCT5104d on apu2 before AmdInitReset, that is why decoding was being enabled here. To be safe with bootblock console init I have added this to southbridge bootblock init: https://review.coreboot.org/c/coreboot/+/37168/17/src/southbridge/amd/pi/hud...
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
Not exactly. LPC decode for SuperIO ports was never there actually. […]
LPC_IO_PORT_DECODE_ENABLE LPC_IO_OR_MEM_DECODE_ENABLE
I did not notice the difference between the two above, specially when it was split across two files.
Once ROMCC_BOOTBLOCK is gone we may want to push more of the implementation into hudson/early_setup.c. This may not be of much importance with APUx (yet) but we should consider cases of size-constrained and read-only bootblocks where console is left uninitialized, and we need that code to run in early romstage.
We had some ideas of keeping only CBMEM console in bootblock and then one could, for debugging purposes, initialize a slow and complex console (SPI flash, EHCI debug) in romstage and replay CBMEM contents then.
We also need to evalute PMxEC bit 0, LPC enable bit. Current implementation inside hudson_lpc_port80() is only conditionally executed.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
LPC_IO_PORT_DECODE_ENABLE […]
This is my bad. I should abstract the SIO LPC decode into hudson_sio_decode_enable() and TPM addresses/ports decoding into hudson_tpm_decode_enable(). I will push a patch for that.
I understand the use-case and it is generally a nice idea.
There should be very little cases where LPC shouldn't be enabled. I think LPC could be enabled by default always. Anything against that idea?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
This is my bad. I should abstract the SIO LPC decode into hudson_sio_decode_enable() and TPM […]
CB:37595 ?
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 35:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
CB:37595 ?
Spotted the change after the comment...
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 36: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
pcengines/apu2: Switch away from ROMCC_BOOTBLOCK
Add early SuperIO initialization in bootblock to enable early console. Also, remove some southbridge-specific initialization that has been moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc A src/mainboard/pcengines/apu2/bootblock.c M src/mainboard/pcengines/apu2/romstage.c 4 files changed, 40 insertions(+), 46 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index b0360cd..8c713e5 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@
config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e..84ea414 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,6 +14,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c new file mode 100644 index 0000000..8318f39 --- /dev/null +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <device/pnp_type.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> + +#define SIO_PORT 0x2e +#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) +#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) + +void bootblock_mainboard_early_init(void) +{ + hudson_lpc_port80(); + hudson_clk_output_48Mhz(); + + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 3e2672a..27f0183 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -14,63 +14,22 @@ */
#include <stdint.h> +#include <amdblocks/acpimmio.h> #include <device/pci_def.h> -#include <arch/io.h> #include <device/pci_ops.h> -#include <device/pnp.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5104d/nct5104d.h> -#include <Fch/Fch.h>
#include "gpio_ftns.h"
-#define SIO_PORT 0x2e -#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) -#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2) - static void early_lpc_init(void);
void board_BeforeAgesa(struct sysinfo *cb) { u32 val; - pci_devfn_t dev; - u32 data;
- /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xd2, 0xcd6); - outb(0x00, 0xcd7); - - post_code(0x30); early_lpc_init();
- hudson_clk_output_48Mhz(); - post_code(0x31); - - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); if (!(val & (1 << 30))) { @@ -78,9 +37,8 @@ pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); }
- /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); + /* Release GPIO32/33 for other uses. */ + pm_write8(0xea, 1); }
static void early_lpc_init(void)
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Paul Menzel (Code Review)