Change in coreboot[master]: google/endeavour: update GPIOs from schematic

[Jeff Chase (Code Review)]

Jeff Chase has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36792 )

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

google/endeavour: update GPIOs from schematic

BUG=b:144307303
TEST=build

Change-Id: Ide216ce1b393c1f49d6e59aa2c84a9a15d009794
---
M src/mainboard/google/fizz/variants/endeavour/gpio.c
1 file changed, 63 insertions(+), 71 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36792/1

diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c
index c11055c..42b0c34 100644
--- a/src/mainboard/google/fizz/variants/endeavour/gpio.c
+++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright 2019 Google Inc.
+ * Copyright 2018 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -40,10 +40,10 @@
 /* SUSACK# */		PAD_CFG_NC(GPP_A15), /* TP150 */
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */		PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */
-/* ISH_GP1 */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */
-/* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
-/* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
+/* ISH_GP0 */		PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
+/* ISH_GP1 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
+/* ISH_GP2 */		PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
+/* ISH_GP3 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
 /* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
 /* ISH_GP5 */		PAD_CFG_NC(GPP_A23),

@@ -57,9 +57,11 @@
 /* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP,
    			   NF1), /* PCIE_CLKREQ_SSD# */
 /* SRCCLKREQ2# */	PAD_CFG_NF(GPP_B7, NONE, DEEP,
-				   NF1), /* PCIE_CLKREQ_NGFF1# */
-/* SRCCLKREQ3# */	PAD_CFG_NC(GPP_B8), /* TP333 */
-/* SRCCLKREQ4# */	PAD_CFG_NC(GPP_B9), /* TP139 */
+				   NF1), /* PCIE_CLKREQ_TPU# */
+/* SRCCLKREQ3# */	PAD_CFG_NF(GPP_B8, NONE, DEEP,
+				   NF1), /* PCIE_CLKREQ_POE# */
+/* SRCCLKREQ4# */	PAD_CFG_NF(GPP_B9, NONE, DEEP,
+				   NF1), /* PCIE_CLKREQ_TPU1# */
 /* SRCCLKREQ5# */	PAD_CFG_NF(GPP_B10, NONE, DEEP,
    			   NF1), /* PCIE_CLKREQ_WLAN# */
 /* EXT_PWR_GATE# */	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */
@@ -74,13 +76,11 @@
    			   NF1), /* PCH_SPI_H1_3V3_MISO */
 /* GSPI0_MOSI */	PAD_CFG_NF(GPP_B18, NONE, DEEP,
    			   NF1), /* PCH_SPI_H1_3V3_MOSI */
-/* GSPI1_CS# */		PAD_CFG_NC(GPP_B19), /* TP111 */
-/* GSPI1_CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU,
-						DEEP), /* VR_DISABLE_L */
-/* GSPI1_MISO */	PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU,
-						DEEP), /* HWA_TRST_N */
+/* GSPI1_CS# */		PAD_CFG_NC(GPP_B19), /* TP98 */
+/* GSPI1_CLK */		PAD_CFG_NC(GPP_B20),
+/* GSPI1_MISO */	PAD_CFG_NC(GPP_B21),
 /* GSPI1_MOSI */	PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */
-/* SML1ALERT# */		PAD_CFG_NC(GPP_B23), /* TP141 */
+/* SML1ALERT# */	PAD_CFG_NC(GPP_B23), /* TP44 */

/* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */
@@ -90,15 +90,11 @@
 /* SML0ALERT# */	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
 /* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU,
    					DEEP), /* EC_IN_RW */
-/* SM1DATA */		PAD_CFG_NC(GPP_C7), /* TP310 */
-/* UART0_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU,
-							DEEP), /* GPIO1 */
-/* UART0_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU,
-							DEEP), /* GPIO2 */
-/* UART0_RTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU,
-						DEEP), /* GPIO3 */
-/* UART0_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU,
-						DEEP), /* GPIO4 */
+/* SM1DATA */		PAD_CFG_NC(GPP_C7), /* TP99 */
+/* UART0_RXD */		PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */		PAD_CFG_NC(GPP_C9),
+/* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
+/* UART0_CTS# */	PAD_CFG_NC(GPP_C11),
 /* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE,
    						DEEP), /* SKU_ID0 */
 /* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE,
@@ -107,21 +103,21 @@
    					DEEP), /* SKU_ID2 */
 /* UART1_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE,
    					DEEP), /* SKU_ID3 */
-/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-/* I2C1_SDA */		PAD_CFG_NC(GPP_C18),
-/* I2C1_SCL */		PAD_CFG_NC(GPP_C19),
+/* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* PCH_I2C_TPU_SDA */
+/* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* PCH_I2C_TPU_SCL */
+/* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SDA */
+/* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_H1_3V3_SCL */
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
-/* UART2_RTS# */	PAD_CFG_NC(GPP_C22), /* TP309 */
+/* UART2_RTS# */	PAD_CFG_NC(GPP_C22), /* TP93 */
 /* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
    			    DEEP), /* SCREW_SPI_WP_STATUS */

-/* SPI1_CS# */		PAD_CFG_NC(GPP_D0), /* TP259 */
-/* SPI1_CLK */		PAD_CFG_NC(GPP_D1), /* TP260 */
-/* SPI1_MISO */		PAD_CFG_NC(GPP_D2), /* TP261 */
-/* SPI1_MOSI */		PAD_CFG_NC(GPP_D3), /* TP262 */
-/* FASHTRIG */		PAD_CFG_NC(GPP_D4), /* TP153 */
+/* SPI1_CS# */		PAD_CFG_NC(GPP_D0), /* TP106 */
+/* SPI1_CLK */		PAD_CFG_NC(GPP_D1), /* TP102 */
+/* SPI1_MISO */		PAD_CFG_NC(GPP_D2), /* TP104 */
+/* SPI1_MOSI */		PAD_CFG_NC(GPP_D3), /* TP105 */
+/* FASHTRIG */		PAD_CFG_NC(GPP_D4), /* TP91 */
 /* ISH_I2C0_SDA */	PAD_CFG_NC(GPP_D5),
 /* ISH_I2C0_SCL */	PAD_CFG_NC(GPP_D6),
 /* ISH_I2C1_SDA */	PAD_CFG_NC(GPP_D7),
@@ -140,57 +136,53 @@
 /* ISH_UART0_CTS# */	PAD_CFG_NC(GPP_D16),
 /* DMIC_CLK1 */		PAD_CFG_NC(GPP_D17),
 /* DMIC_DATA1 */	PAD_CFG_NC(GPP_D18),
-/* DMIC_CLK0 */		PAD_CFG_NC(GPP_D19), /* TP121 */
-/* DMIC_DATA0 */	PAD_CFG_NC(GPP_D20), /* TP122 */
-/* SPI1_IO2 */		PAD_CFG_NC(GPP_D21), /* TP257 */
-/* SPI1_IO3 */		PAD_CFG_NC(GPP_D22), /* TP258 */
+/* DMIC_CLK0 */		PAD_CFG_NC(GPP_D19), /* TP100 */
+/* DMIC_DATA0 */	PAD_CFG_NC(GPP_D20), /* TP90 */
+/* SPI1_IO2 */		PAD_CFG_NC(GPP_D21), /* TP101 */
+/* SPI1_IO3 */		PAD_CFG_NC(GPP_D22), /* TP94 */
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */

/* SATAXPCI0 */		PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE,
    					PLTRST), /* H1_PCH_INT_ODL */
 /* SATAXPCIE1 */	PAD_CFG_NF(GPP_E1, NONE, DEEP,
    			   NF1), /* MB_PCIE_SATA#_DET */
-/* SATAXPCIE2 */	PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
-				   NF1), /* DB_PCIE_SATA#_DET */
-/* CPU_GP0 */		PAD_CFG_NC(GPP_E3),
+/* SATAXPCIE2 */	PAD_CFG_NC(GPP_E2),
+/* CPU_GP0 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP,
+             NONE), /* TPU_RST_PIN40 */
 /* SATA_DEVSLP0 */	PAD_CFG_NC(GPP_E4), /* TP103 */
 /* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
 /* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */
-/* CPU_GP1 */		PAD_CFG_NC(GPP_E7),
-/* SATALED# */		PAD_CFG_NC(GPP_E8), /* TP314 */
-/* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
-/* USB2_OC1# */		PAD_CFG_NF(GPP_E10, NONE, DEEP,
-					NF1), /* Rear Dual-Stack USB Ports */
+/* CPU_GP1 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP,
+             NONE), /* TPU_RST_PIN42 */
+/* SATALED# */		PAD_CFG_NC(GPP_E8), /* TP96 */
+/* USB2_OCO# */		PAD_CFG_NC(GPP_E9), /* T1037 */
+/* USB2_OC1# */		PAD_CFG_NC(GPP_E10), /* T1025 */
 /* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP,
-					   NF1), /* Front USB Ports */
+					   NF1), /* Rear Dual-Stack USB Ports */
 /* USB2_OC3# */		PAD_CFG_NF(GPP_E12, NONE, DEEP,
    				   NF1), /* Rear Single USB Port */
 /* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP,
-					   NF1), /* INT_HDMI_HPD */
+					   NF1), /* DDI1_HDMI_HPD */
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP,
-					   NF1), /* DDI2_HPD */
-/* DDPD_HPD2 */		PAD_CFG_NC(GPP_E15), /* TP325 */
-/* DDPE_HPD3 */		PAD_CFG_NC(GPP_E16), /* TP326 */
+					   NF1), /* DDI2_HDMI_HPD */
+/* DDPD_HPD2 */		PAD_CFG_GPI_APIC(GPP_E15, NONE, DEEP), /* PCH_TYPEC_UPFB */
+/* DDPE_HPD3 */		PAD_CFG_NC(GPP_E16), /* TP1021 */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP,
-				   NF1), /* HDMI_DDCCLK_SW */
-/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, 20K_PD, DEEP,
-				   NF1), /* HDMI_DDCCLK_DATA */
-/* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */
-/* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */
+/* DDPB_CTRLCLK */	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_DDCCLK_SW */
+/* DDPB_CTRLDATA */	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_DDCCLK_DATA */
+/* DDPC_CTRLCLK */	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDI2_DDCCLK_SW */
+/* DDPC_CTRLDATA */	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDI2_DDCDATA_SW */
 /* DDPD_CTRLCLK */	PAD_CFG_NC(GPP_E22),
 /* DDPD_CTRLDATA */	PAD_CFG_NC(GPP_E23),

-/* I2S2_SCLK */		PAD_CFG_NC(GPP_F0), /* TP191 */
-/* I2S2_SFRM */		PAD_CFG_NC(GPP_F1), /* TP192 */
-/* I2S2_TXD */		PAD_CFG_NC(GPP_F2), /* TP190 */
-/* I2S2_RXD */		PAD_CFG_NC(GPP_F3), /* TP189 */
-/* I2C2_SDA */		PAD_CFG_NF(GPP_F4, NONE, DEEP,
-				   NF1), /* PCH_I2C2_H1_3V3_SDA */
-/* I2C2_SCL */		PAD_CFG_NF(GPP_F5, NONE, DEEP,
-				   NF1), /* PCH_I2C2_H1_3V3_SCL */
-/* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
-/* I2C3_SCL */		PAD_CFG_NC(GPP_F7),
+/* I2S2_SCLK */		PAD_CFG_NC(GPP_F0), /* TP43 */
+/* I2S2_SFRM */		PAD_CFG_NC(GPP_F1), /* TP48 */
+/* I2S2_TXD */		PAD_CFG_NC(GPP_F2), /* TP42 */
+/* I2S2_RXD */		PAD_CFG_NC(GPP_F3), /* TP37 */
+/* I2C2_SDA */		PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */		PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */		PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* DDI1_I2C_7322_SDA */
+/* I2C3_SCL */		PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* DDI1_I2C_7322_SCL */
 /* I2C4_SDA */		PAD_CFG_NC(GPP_F8),
 /* I2C4_SCL */		PAD_CFG_NC(GPP_F9),
 /* I2C5_SDA */		PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP,
@@ -217,19 +209,19 @@
 /* SD_DATA3 */		PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 /* SD_CD# */		PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */
 /* SD_CLK */		PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
-/* SD_WP */		PAD_CFG_NC(GPP_G7), /* TP292 */
+/* SD_WP */		PAD_CFG_NC(GPP_G7), /* TP40 */

-/* BATLOW# */		PAD_CFG_NC(GPD0), /* TP148 */
+/* BATLOW# */		PAD_CFG_NC(GPD0), /* TP23 */
 /* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */
 /* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */
 /* PWRBTN# */		PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */
 /* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */
 /* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */
-/* SLP_A# */		PAD_CFG_NC(GPD6), /* TP147 */
+/* SLP_A# */		PAD_CFG_NC(GPD6), /* TP22 */
 /* RSVD */		PAD_CFG_NC(GPD7),
 /* SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */
-/* SLP_WLAN# */		PAD_CFG_NC(GPD9), /* TP146 */
-/* SLP_S5# */		PAD_CFG_NC(GPD10), /* TP143 */
+/* SLP_WLAN# */		PAD_CFG_NC(GPD9), /* TP83 */
+/* SLP_S5# */		PAD_CFG_NC(GPD10), /* TP84 */
 /* LANPHYC */		PAD_CFG_NC(GPD11),
 };

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36792 )

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
File src/mainboard/google/fizz/variants/endeavour/gpio.c:

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 151:              NONE), /* TPU_RST_PIN40 */
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 151:              NONE), /* TPU_RST_PIN40 */
please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 156:              NONE), /* TPU_RST_PIN42 */
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 156:              NONE), /* TPU_RST_PIN42 */
please, no spaces at the start of a line

[Jeff Chase (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36792

to look at the new patch set (#2).

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

google/endeavour: update GPIOs from schematic

BUG=b:144307303
TEST=build

Change-Id: Ide216ce1b393c1f49d6e59aa2c84a9a15d009794
Signed-off-by: Jeff Chase 
---
M src/mainboard/google/fizz/variants/endeavour/gpio.c
1 file changed, 63 insertions(+), 71 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36792/2

[Jeff Chase (Code Review)]

Jeff Chase has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36792 )

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

Patch Set 2:

(4 comments)

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
File src/mainboard/google/fizz/variants/endeavour/gpio.c:

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 151:              NONE), /* TPU_RST_PIN40 */
> code indent should use tabs where possible

Done

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 151:              NONE), /* TPU_RST_PIN40 */
> please, no spaces at the start of a line

Done

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 156:              NONE), /* TPU_RST_PIN42 */
> code indent should use tabs where possible

Done

https://review.coreboot.org/c/coreboot/+/36792/1/src/mainboard/google/fizz/v... 
PS1, Line 156:              NONE), /* TPU_RST_PIN42 */
> please, no spaces at the start of a line

Done

[Jeff Chase (Code Review)]

Hello Shelley Chen, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36792

to look at the new patch set (#4).

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

google/endeavour: update GPIOs from schematic

BUG=b:144307303
TEST=build

Change-Id: Ide216ce1b393c1f49d6e59aa2c84a9a15d009794
Signed-off-by: Jeff Chase 
---
M src/mainboard/google/fizz/variants/endeavour/gpio.c
1 file changed, 63 insertions(+), 71 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36792/4

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36792 )

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

Patch Set 4:

I would squash this into CB:36791, so that CB:36791 can be boot-tested and merged in knowing that it works.

[Jeff Chase (Code Review)]

Jeff Chase has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36792 )

Change subject: google/endeavour: update GPIOs from schematic
......................................................................

Abandoned

Squashed into CB:36791