Change in coreboot[master]: google/endeavour: update overridetree.cb

[Jeff Chase (Code Review)]

Jeff Chase has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36933 )

Change subject: google/endeavour: update overridetree.cb
......................................................................

google/endeavour: update overridetree.cb

BUG=b:144307303
TEST=build

Change-Id: I036703f5269cd6ca92514db76f5b34d029173a71
Signed-off-by: Jeff Chase 
---
M src/mainboard/google/fizz/variants/endeavour/gpio.c
M src/mainboard/google/fizz/variants/endeavour/overridetree.cb
2 files changed, 111 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/36933/1

diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c
index 4ae954c..3779a59 100644
--- a/src/mainboard/google/fizz/variants/endeavour/gpio.c
+++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c
@@ -42,8 +42,8 @@
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
 /* ISH_GP0 */		PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
 /* ISH_GP1 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
-/* ISH_GP2 */		PAD_CFG_GPI_APIC(GPP_A18, NONE, DEEP), /* 7322_INTO */
-/* ISH_GP3 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */
+/* ISH_GP2 */		PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP), /* 7322_INTO */
+/* ISH_GP3 */		PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */
 /* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
 /* ISH_GP5 */		PAD_CFG_NC(GPP_A23),

diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
index 500e6cf..1a6b2f4 100644
--- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb
@@ -1,4 +1,112 @@
 chip soc/intel/skylake
+
+	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# HDMI
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC2)"		# Type-A Rear
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC2)"		# Type-A Rear
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC3)"		# Type-A Rear
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# HDMI Audio
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"		# None
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"		# H1 (disconnected)
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# HDMI
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# Type-A Rear
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)"	# Type-A Rear
+	register "usb3_ports[5]" = "USB3_PORT_EMPTY"	# None
+
+	register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3"		# TPU
+	register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3"		# TPM
+	register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8"		# None
+	register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8"		# HDMI
+	register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8"		# Audio
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexSpi0]  = PchSerialIoPci,
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexUart0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+	}"
+
    device domain 0 on
-  end
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 HDMI In""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Rear Left""
+						register "type" = "UPC_TYPE_A"
+						device usb 2.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Rear Middle""
+						register "type" = "UPC_TYPE_A"
+						device usb 2.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 HDMI Audio In""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 HDMI In""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Front Right""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 3.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Front Left""
+						register "type" = "UPC_TYPE_USB3_A"
+						device usb 3.3 on end
+					end
+				end
+			end
+		end # USB xHCI
+		device pci 15.3 on
+			chip drivers/i2c/generic
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "name" = ""CH72""
+				register "desc" = ""Chrontel 7322""
+				register "uid" = "1"
+				register "compat_string" = ""chrontel,7322""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A18)"
+				device i2c 75 on end
+			end
+			chip drivers/i2c/generic
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "name" = ""CH72""
+				register "desc" = ""Chrontel 7322""
+				register "uid" = "2"
+				register "compat_string" = ""chrontel,7322""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)"
+				device i2c 76 on end
+			end
+		end # I2C #3
+		device pci 19.1 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5663""
+				register "name" = ""RT53""
+				register "desc" = ""Realtek RT5663""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
+				device i2c 13 on end
+			end
+		end # I2C #5
+	end
 end

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36933 )

Change subject: google/endeavour: update overridetree.cb
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36933/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36933/1//COMMIT_MSG@8 
PS1, Line 8: 
You also change GPIOs.

[Jeff Chase (Code Review)]

Jeff Chase has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36933 )

Change subject: google/endeavour: update overridetree.cb
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36933/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/36933/1//COMMIT_MSG@8 
PS1, Line 8:
> You also change GPIOs.

Moved the GPIO fix to the previous change

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36933 )

Change subject: google/endeavour: update overridetree.cb
......................................................................

Patch Set 2:

I would squash this into CB:36791, so that CB:36791 can be boot-tested and merged in knowing that it works.

[Jeff Chase (Code Review)]

Jeff Chase has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/36933 )

Change subject: google/endeavour: update overridetree.cb
......................................................................

Abandoned

Squashed into CB:36791