[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for SPI RW

[Ashish Kumar Mishra (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph, Paul Menzel, Saurabh Mishra, Subrata Banik.

Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email )

Change subject: block/fast_spi: Use read32p/write32p for SPI RW
......................................................................

Patch Set 5:

(3 comments)

File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:

https://review.coreboot.org/c/coreboot/+/82079/comment/b9d6f896_dfbf38cb :
PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data;
            : 	size_t bytes_to_copy;
            : 	union {
            : 		uint32_t full;
            : 		uint8_t bytes[4];
            : 	} dword;
            : 
            : 	for (size_t i = 0; i < len; i += 4) {
            : 		dword.full = 0;
            : 
            : 		bytes_to_copy = (len - i < 4) ? len - i : 4;
            : 		for (size_t j = 0; j < bytes_to_copy; j++)
            : 			dword.bytes[j] = byte_ptr[i + j];
            : 
            : 		write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full);
            : 	}
> OK. Marking this as unresolved until the patch is actually updated.

Done

File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:

https://review.coreboot.org/c/coreboot/+/82079/comment/3373f537_8c4fd3e5 :
PS4, Line 81: (len >> 2)
> This optimisation can be done by the compiler. […]

Done

https://review.coreboot.org/c/coreboot/+/82079/comment/ac00e240_abdca429 :
PS4, Line 85: (len & 3)
> Same here, please use `len % 4`

Done