Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
[WIP] hudson_lpc_port80
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu2/bootblock.c M src/southbridge/amd/agesa/hudson/bootblock.c 21 files changed, 5 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37451/1
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c9a257c..58430dc 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -29,8 +29,6 @@ { u32 val;
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 475431e..a0c6b8d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 4dde4e2..7f37990 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -48,8 +48,6 @@ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
- hudson_lpc_port80(); - if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9a28f98..122bb19 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -41,8 +41,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ for (i = 0; i < 200000; i++) val = inb(0xcd6); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index bb80687..c04aafe 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 48aee89..6366c4e 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -19,8 +19,6 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); - pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* For serial port option, plug-in card on LPC. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1d89e4d..5678021 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@
/* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - hudson_lpc_port80();
byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index ce5e064..5b9a226 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,8 +35,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 5e1218a..fff760b 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -144,8 +144,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d5acdb5..8a48e00 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -68,11 +68,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index ef7a7fb..505de38 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -36,7 +36,5 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e58f875..de39f18 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,8 +41,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index ddcf4d0..5d210fa 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -58,12 +58,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - - if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index c83a865..6c1581b 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -89,8 +89,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index c656347..4676199 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -24,8 +24,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 2cc8d1b..d7322c9 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -32,8 +32,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 0266eff..ebb875d 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,11 +117,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c index 8318f39..7a5d84e 100644 --- a/src/mainboard/pcengines/apu2/bootblock.c +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -23,7 +23,6 @@
void bootblock_mainboard_early_init(void) { - hudson_lpc_port80(); hudson_clk_output_48Mhz();
/* COM2 on apu5 is reserved so only COM1 should be supported */ diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 97e8803..e3e055e 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -77,6 +77,11 @@ hudson_lpc_decode(); enable_acpimmio_decode_pm24();
+ if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 81: hudson_pci_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 81: hudson_pci_port80(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 82: else if (CONFIG(POST_DEVICE_LPC)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 82: else if (CONFIG(POST_DEVICE_LPC)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 83: hudson_lpc_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/1/src/southbridge/amd/agesa/h... PS1, Line 83: hudson_lpc_port80(); please, no spaces at the start of a line
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 1:
looks like there are whitespace issues
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 1:
You missed sb/amd/pi/hudson
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 2:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 81: hudson_pci_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 81: hudson_pci_port80(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 82: else if (CONFIG(POST_DEVICE_LPC)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 82: else if (CONFIG(POST_DEVICE_LPC)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 83: hudson_lpc_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/2/src/southbridge/amd/agesa/h... PS2, Line 83: hudson_lpc_port80(); please, no spaces at the start of a line
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 3:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 81: hudson_pci_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 81: hudson_pci_port80(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 82: else if (CONFIG(POST_DEVICE_LPC)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 82: else if (CONFIG(POST_DEVICE_LPC)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 83: hudson_lpc_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/3/src/southbridge/amd/agesa/h... PS3, Line 83: hudson_lpc_port80(); please, no spaces at the start of a line
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 4:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 81: hudson_pci_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 81: hudson_pci_port80(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 82: else if (CONFIG(POST_DEVICE_LPC)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 82: else if (CONFIG(POST_DEVICE_LPC)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 83: hudson_lpc_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/4/src/southbridge/amd/agesa/h... PS4, Line 83: hudson_lpc_port80(); please, no spaces at the start of a line
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 80: if (CONFIG(POST_DEVICE_PCI_PCIE)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 81: hudson_pci_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 81: hudson_pci_port80(); please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 82: else if (CONFIG(POST_DEVICE_LPC)) please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 82: else if (CONFIG(POST_DEVICE_LPC)) suspect code indent for conditional statements (7, 15)
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 83: hudson_lpc_port80(); code indent should use tabs where possible
https://review.coreboot.org/c/coreboot/+/37451/5/src/southbridge/amd/agesa/h... PS5, Line 83: hudson_lpc_port80(); please, no spaces at the start of a line
Hello Alexander Couzens, Patrick Rudolph, Piotr Król, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37451
to look at the new patch set (#6).
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day.
This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/pi/hudson/bootblock.c 39 files changed, 27 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37451/6
Hello Alexander Couzens, Patrick Rudolph, Piotr Król, Angel Pons, build bot (Jenkins), Michał Żygowski,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37451
to look at the new patch set (#7).
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day.
This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/console/Kconfig M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/pi/hudson/bootblock.c 40 files changed, 32 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37451/7
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/lenovo/g505s/... File src/mainboard/lenovo/g505s/romstage.c:
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/lenovo/g505s/... PS7, Line 19: void board_BeforeAgesa(struct sysinfo *cb) Can we make this a 1-liner?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/lenovo/g505s/... File src/mainboard/lenovo/g505s/romstage.c:
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/lenovo/g505s/... PS7, Line 19: void board_BeforeAgesa(struct sysinfo *cb)
Can we make this a 1-liner?
File gets removed with a nearby commit.
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
Patch Set 7: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/asrock/imb-a1... File src/mainboard/asrock/imb-a180/romstage.c:
https://review.coreboot.org/c/coreboot/+/37451/7/src/mainboard/asrock/imb-a1... PS7, Line 34: /* Set LPC decode enables. */ Another point to remove in the near future. Other boards may as well have these LPC and ACPI MMIO decode-enables. To be revisited.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: AGESA,binaryPI: Move PORT80 selection to C bootblock ......................................................................
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day.
This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/console/Kconfig M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehill/Kconfig M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/Kconfig M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/thatcher/Kconfig M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/Kconfig M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e20XX/Kconfig M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gizmosphere/gizmo2/Kconfig M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/hp/abm/Kconfig M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/Kconfig M src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/g505s/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/romstage.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/pi/hudson/bootblock.c 40 files changed, 32 insertions(+), 47 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/console/Kconfig b/src/console/Kconfig index 9151a32..5225d11 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -417,6 +417,7 @@ choice prompt "Device to send POST codes to" depends on POST_DEVICE + default POST_DEVICE_LPC if DEFAULT_POST_ON_LPC default POST_DEVICE_NONE
config POST_DEVICE_NONE @@ -429,6 +430,10 @@ depends on PCI endchoice
+config DEFAULT_POST_ON_LPC + bool + default n + config POST_IO bool "Send POST codes to an IO port" depends on PC80_SYSTEM && !NO_POST diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index f5f37ce..08410d3 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -25,6 +25,7 @@ select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c9a257c..58430dc 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -29,8 +29,6 @@ { u32 val;
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index b83a525..eb5fe87 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -26,6 +26,7 @@ select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 475431e..a0c6b8d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index 1d3e0f6..d509afc 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -25,6 +25,7 @@ select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON + select DEFAULT_POST_ON_LPC select SUPERIO_FINTEK_F81216H select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 4dde4e2..7f37990 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -48,8 +48,6 @@ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
- hudson_lpc_port80(); - if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index 806fdbd..e1b5215 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -21,6 +21,7 @@ select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9a28f98..122bb19 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -41,8 +41,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ for (i = 0; i < 200000; i++) val = inb(0xcd6); diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 230dc4b..229e3f9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -25,6 +25,7 @@ select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index bb80687..c04aafe 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index dde58a6..3b6cb5c 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -21,6 +21,7 @@ select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 48aee89..6366c4e 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -19,8 +19,6 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); - pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* For serial port option, plug-in card on LPC. */ diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e11d0ea..2c0939c 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -21,6 +21,7 @@ select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1d89e4d..5678021 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@
/* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - hudson_lpc_port80();
byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index 883b1c0..b753424 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -21,6 +21,7 @@ select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_WINBOND_W83627UHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index ce5e064..5b9a226 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,8 +35,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index c3f21e9..f194519 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -16,6 +16,7 @@ select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_ITE_IT8623E select MAINBOARD_HAS_LPC_TPM
diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index c0f5c04..de85325 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -142,8 +142,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d5acdb5..8a48e00 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -68,11 +68,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index a62fba8..97593d5 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -22,6 +22,7 @@ select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index ef7a7fb..505de38 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -36,7 +36,5 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 3705fb9..bc5c131 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -25,6 +25,7 @@ select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e58f875..de39f18 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,8 +41,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index ddcf4d0..5d210fa 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -58,12 +58,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - - if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 4ea5ddc..3c87965 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -30,6 +30,7 @@ select HAVE_ACPI_TABLES select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_ITE_IT8728F
config MAINBOARD_DIR diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index c83a865..6c1581b 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -89,8 +89,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 27a3b35..b066cdb 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -22,6 +22,7 @@ select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index c656347..4676199 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -24,8 +24,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index a179dbe..9e35163 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -22,6 +22,7 @@ select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 2cc8d1b..d7322c9 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -32,8 +32,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 05ea52f..144b113 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -22,6 +22,7 @@ select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 815c7d5..b220b97 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -22,6 +22,7 @@ select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 0266eff..ebb875d 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,11 +117,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 5ecdb88..b0360cd 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -24,6 +24,7 @@ select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select SUPERIO_NUVOTON_NCT5104D select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6c97c57..3e2672a 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -52,8 +52,6 @@ outb(0xd2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - post_code(0x30); early_lpc_init();
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 97e8803..6925393 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -77,6 +77,11 @@ hudson_lpc_decode(); enable_acpimmio_decode_pm24();
+ if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */ diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index e9a9d33..ec8663d 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -79,6 +79,11 @@ else enable_acpimmio_decode_pm04();
+ if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */
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