Change in coreboot[master]: cpu/intel/common: Report the CPU max speed in SMBIOS

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

cpu/intel/common: Report the CPU max speed in SMBIOS

Use the TSC frequency to provide the maximum processor speed in
SMBIOS tables type 4. The TSC frequency is the "Maximum Non-Turbo Ratio"
or "Scaleable Bus Speed" on older platforms, times the FSB.

Change-Id: I8030187d2c9714c7f6c9451fd2318b3c6608e431
Signed-off-by: Patrick Rudolph 
---
M src/cpu/intel/common/fsb.c
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43903/1

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
index 7772171..df2e51c 100644
--- a/src/cpu/intel/common/fsb.c
+++ b/src/cpu/intel/common/fsb.c
@@ -7,6 +7,7 @@
 #include <console/console.h>
 #include <commonlib/helpers.h>
 #include <delay.h>
+#include <smbios.h>

static u32 timer_fsb;
 static u32 timer_tsc;
@@ -137,3 +138,17 @@
    printk(BIOS_ERR, "FSB not supported or not found\n");
    return -1;
 }
+
+#if CONFIG(GENERATE_SMBIOS_TABLES)
+unsigned int smbios_cpu_get_max_speed_mhz(void)
+{
+	int ret, fsb, ratio;
+
+	/* Return the Maximum Non-Turbo Ratio (R/O) */
+	ret = get_fsb_tsc(&fsb, &ratio);
+	if (ret == 0)
+		return fsb * ratio;
+
+	return 0;
+}
+#endif

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/43903/1/src/cpu/intel/common/fsb.c 
File src/cpu/intel/common/fsb.c:

https://review.coreboot.org/c/coreboot/+/43903/1/src/cpu/intel/common/fsb.c@... 
PS1, Line 148: ret
Drop the intermediate variable?

[Marcello Sylvester Bauer (Code Review)]

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Patch Set 1: Code-Review+1

diff `dmidecode -t4` on a thinkPad X220:

```
3c3
< SMBIOS 2.8 present.
---
> SMBIOS 3.0 present.

5c5
< Handle 0x0004, DMI type 4, 42 bytes
---
> Handle 0x0004, DMI type 4, 48 bytes

45c45
< 	Max Speed: Unknown
---
> Max Speed: 2600 MHz

47c47
< 	Status: Populated, Enabled
---
> Status: Unpopulated

```

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Angel Pons,  Marcello Sylvester Bauer, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43903

to look at the new patch set (#2).

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

cpu/intel/common: Report the CPU max speed in SMBIOS

Use the TSC frequency to provide the maximum processor speed in
SMBIOS tables type 4. The TSC frequency is the "Maximum Non-Turbo Ratio"
or "Scaleable Bus Speed" on older platforms, times the FSB.

Change-Id: I8030187d2c9714c7f6c9451fd2318b3c6608e431
Signed-off-by: Patrick Rudolph 
---
M src/cpu/intel/common/fsb.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43903/2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/43903/1/src/cpu/intel/common/fsb.c 
File src/cpu/intel/common/fsb.c:

https://review.coreboot.org/c/coreboot/+/43903/1/src/cpu/intel/common/fsb.c@... 
PS1, Line 148: ret
> Drop the intermediate variable?

Done

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG@10 
PS2, Line 10: tables type 4
nit: type 4 tables

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG@11 
PS2, Line 11: Scaleable
no `e`: Scalable

[Angel Pons (Code Review)]

Angel Pons has uploaded a new patch set (#3) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

cpu/intel/common: Report the CPU max speed in SMBIOS

Use the TSC frequency to provide the maximum processor speed in
SMBIOS type 4 tables. The TSC frequency is the "Maximum Non-Turbo Ratio"
or "Scalable Bus Speed" on older platforms, times the FSB.

Change-Id: I8030187d2c9714c7f6c9451fd2318b3c6608e431
Signed-off-by: Patrick Rudolph 
---
M src/cpu/intel/common/fsb.c
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43903/3

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43903 )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG@10 
PS2, Line 10: tables type 4
> nit: type 4 tables

Done

https://review.coreboot.org/c/coreboot/+/43903/2//COMMIT_MSG@11 
PS2, Line 11: Scaleable
> no `e`: Scalable

Done

[S] Change in coreboot[master]: cpu/intel/common: Report the CPU max speed in SMBIOS

[Martin L Roth (Code Review)]

Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43903?usp=email )

Change subject: cpu/intel/common: Report the CPU max speed in SMBIOS
......................................................................

Abandoned

This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.