Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mainboard: Add Acer ES1-572 ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere.
yes but no. […]
ACPI code needs to be added to communicate with the EC. Check the vendor's DSDT
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 266: device pci 1f.5 off end # PCH SPI
breaks rom console, too
Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. Is there any reason why this is the case, or should we fix it (preferably with a check against a lockdown related config, CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION or CB:32704)?
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Benjamin Doron (Code Review)