Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS setting

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Wonkyu Kim (Code Review)

29 Jan 2020 29 Jan '20

7:18 a.m.

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3f980d1..a4542fb 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -218,6 +218,34 @@ FORCE_ENABLE, } CnviBtAudioOffload;

+ /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + + /* + * Tcss Aux Orienation override + * bits 0, 2, ... 10 control override for port + * value: 1 - controlled by iom, 0 - controled by retimer + * bits 1, 3, ... 11 orientation override for port + * value: 0 - not swapped , 1 - swapped + * Reference: IOM_TYPEC_SW_CONFIGURATION_3 in TGL EDS#575681 + */ + uint8_t TcssAuxOri; + + /* + * Tcss HSL Orientation override + * bits 0, 2, ... 10 control override for port + * bits 1, 3, ... 11 orientation override for port + * Reference: IOM_TYPEC_SW_CONFIGURATION_4 in TGL EDS#575681 + */ + uint8_t TcssHslOri; + + /* + * TypeC port GPIO setting + * GPIO pin number for Type C Aux orienation setting when it's controlled by iom + */ + uint32_t IomTypeCPortPadCfg[8]; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..085689c 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,12 @@ sizeof(params->SataPortsDevSlp)); }

+ /* Tcss */ + params->TcssHslOri = config->TcssHslOri; + params->TcssAuxOri = config->TcssAuxOri; + memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, + sizeof(config->IomTypeCPortPadCfg)); + mainboard_silicon_init_params(params); }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 6ed3dcd..88c790b 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -102,6 +102,10 @@ m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;

+ /* Tcss */ + m_cfg->TcssXhciEn = config->TcssXhciEn; + m_cfg->TcssXdciEn = config->TcssXdciEn; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */

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build bot (Jenkins) (Code Review)

29 Jan 29 Jan

7:18 a.m.

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 1:

(8 comments)

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 222: uint8_t TcssXhciEn; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 222: uint8_t TcssXhciEn; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 223: uint8_t TcssXdciEn; code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 223: uint8_t TcssXdciEn; please, no spaces at the start of a line

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 228: * value: 1 - controlled by iom, 0 - controled by retimer 'controled' may be misspelled - perhaps 'controlled'?

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 228: * value: 1 - controlled by iom, 0 - controled by retimer please, no space before tabs

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 230: * value: 0 - not swapped , 1 - swapped please, no space before tabs

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 235: /* trailing whitespace

Wonkyu Kim (Code Review)

7:23 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/2

Wonkyu Kim (Code Review)

7:23 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 2:

(8 comments)

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 222: uint8_t TcssXhciEn;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 222: uint8_t TcssXhciEn;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 223: uint8_t TcssXdciEn;

...

code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 223: uint8_t TcssXdciEn;

...

please, no spaces at the start of a line

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 228: * value: 1 - controlled by iom, 0 - controled by retimer

...

'controled' may be misspelled - perhaps 'controlled'?

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 228: * value: 1 - controlled by iom, 0 - controled by retimer

...

please, no space before tabs

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 230: * value: 0 - not swapped , 1 - swapped

...

please, no space before tabs

Ack

https://review.coreboot.org/c/coreboot/+/38624/1/src/soc/intel/tigerlake/chi... PS1, Line 235: /*

...

trailing whitespace

Ack

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-Comment-Date: Wed, 29 Jan 2020 06:23:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) no-reply@coreboot.org Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

7:25 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/3

Wonkyu Kim (Code Review)

7:27 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 3: Code-Review+1

Furquan Shaikh (Code Review)

7:51 a.m.

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri Why do these have to be done by FSP? These are documented EDS registers which can be set by coreboot.

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg)); Have you tried doing: memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));

to see if it boots fine without the assert? and ensure that the required pads are configured before calling into FSP-S?

Wonkyu Kim (Code Review)

8:47 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

Why do these have to be done by FSP? These are documented EDS registers which can be set by coreboot […]

According to FSP code, the UPD is interface for writing value in IOM_TYPEC_SW_CONFIGURATION_3 according to board design. So I added EDS info as reference for value of this UPD. I think we don't have any issue to use the UPD.

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));

...

Have you tried doing: […]

We already check if it's possible like Image clock or ISH pins but it's not only for pin mux. The UPD is also used for writing IOM register for IOM to controll the GPIO as AUXP_DC and AUXN_DC as there are many GPIOs options which IOM can use. for GPIO options for IOM to use, refer NF6 for each GPIO in pin mux table.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-Comment-Date: Wed, 29 Jan 2020 07:47:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

7:48 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/4

Wonkyu Kim (Code Review)

7:49 p.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 4: Code-Review+1

Rebase to fix merge conflict

Pratikkumar V Prajapati (Code Review)

9:03 p.m.

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 4: 2019 2019-2020

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/fsp... PS4, Line 4: 2019 2019-2020

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Wed, 29 Jan 2020 20:03:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Furquan Shaikh (Code Review)

9:35 p.m.

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

According to FSP code, the UPD is interface for writing value in IOM_TYPEC_SW_CONFIGURATION_3 accord […]

My point is why does coreboot not write to this register directly instead of setting the UPD?

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));

...

We already check if it's possible like Image clock or ISH pins but it's not only for pin mux. […]

Same question as before. Even if there are multiple options, can't those be configured in coreboot? Also, if there are IOM registers that need to be set, coreboot should be able to do it. I don't agree with the setting of magic values as pad cfgs in UPDs to make FSP do the work which coreboot can do itself.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Wed, 29 Jan 2020 20:35:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim wonkyu.kim@intel.com Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

30 Jan 30 Jan

8:26 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 4:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

My point is why does coreboot not write to this register directly instead of setting the UPD?

Yes. it's doable but takes time as all IOM registers are not available in current EDS. IOM register which assign GPIO is not avaiable. So, can we merge as it is(using FSP UPD) and implement IOM register later when new EDS is available? I'll create partner bug for this for track it. what do you think?

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));

...

Same question as before. […]

Yes. it's doable but takes time as the register info for assign GPIO is not available EDS yet. We already request EDS owner open up the issue. So, can we merge as it is(using FSP UPD) and implement IOM register later when new EDS is available? I'll create partner bug for this for track it. what do you think?

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Thu, 30 Jan 2020 07:26:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim wonkyu.kim@intel.com Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Paul Menzel (Code Review)

10:32 a.m.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38624/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38624/4//COMMIT_MSG@9 PS4, Line 9: Xhci xHCI

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 226: Orienation Orientation

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 245: orienation orientation

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Thu, 30 Jan 2020 09:32:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

31 Jan 31 Jan

11:23 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure Xhci, Xdci, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/5

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

11:23 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure xHCI, xDCI, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/6

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 6 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

11:27 a.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure xHCI, xDCI, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/7

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

11:28 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 7:

(5 comments)

https://review.coreboot.org/c/coreboot/+/38624/4//COMMIT_MSG Commit Message:

https://review.coreboot.org/c/coreboot/+/38624/4//COMMIT_MSG@9 PS4, Line 9: Xhci

...

xHCI

Done

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 4: 2019

...

2019-2020

Done

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 226: Orienation

...

Orientation

Done

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/chi... PS4, Line 245: orienation

...

orientation

Done

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/4/src/soc/intel/tigerlake/fsp... PS4, Line 4: 2019

...

2019-2020

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 10:28:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Comment-In-Reply-To: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

11:29 a.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 7: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 10:29:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Furquan Shaikh (Code Review)

4:52 p.m.

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

Yes. it's doable but takes time as all IOM registers are not available in current EDS. […]

The only registers that I see not documented are the GPIO related. Can we keep the IomTypeCPortPadCfg until the EDS issue is resolved, but not do the TcssAuxOri and TcssHslOri using FSP UPD?

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 15:52:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim wonkyu.kim@intel.com Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

7:58 p.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 7: -Code-Review

(1 comment)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

The only registers that I see not documented are the GPIO related. […]

Sure, I'll create partnerbug implemenation for TcssAuxOri and TcssHslOri and start working. So, it should be 2 partnerbug. (TcssAuxOri/TcssHslOri and IomTypeCPortPadCfg) BTW, I think chip.h variables should be remain for mainboard(devicetree)to pass register values. Or do you have any other thought to pass register values?

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Wonkyu Kim (Code Review)

8:03 p.m.

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

Patch Set 7:

This change is ready for review.

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Wonkyu Kim (Code Review)

8:05 p.m.

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#8).

Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................

soc/intel/tigerlake: Configure TCSS setting

Configure xHCI, xDCI, Aux/Hsl orientation for TCSS according to board design. - Enable/Disable Xhci/Xdci - Configure Aux/Hsl orientation according to TGL EDS#575681

BUG=none BRANCH=none TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/8

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 8 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

8:06 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#9).

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Configure xHCI, xDCI according to board design

BUG=none BRANCH=none TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/9

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 9 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

8:07 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 9:

Update patch only configure TCSS xHCI and xDCI, TypeC orientation configuration will be done in different patch.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 9 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 19:07:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

8:08 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38624

to look at the new patch set (#10).

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Configure xHCI, xDCI according to board design

BUG=none BRANCH=none TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38624/10

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: newpatchset

Wonkyu Kim (Code Review)

8:09 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 10:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

Sure, I'll create partnerbug implemenation for TcssAuxOri and TcssHslOri and start working. […]

Done

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg));

...

Yes. it's doable but takes time as the register info for assign GPIO is not available EDS yet. […]

Done

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Wonkyu Kim (Code Review)

8:21 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 10: Code-Review+1

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 19:21:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Furquan Shaikh (Code Review)

8:47 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

Done

partner bug - I think it can be done as part of the same bug for TCSS enabling. For IomCPortPadCfg -- yes, a separate bug is required to capture the progress of adding registers to EDS and adding support to coreboot for doing the configuration.

About keeping the params in chip.h -- Sure. I haven't looked at all the details of the register bits yet, but some information will be required from mainboard to do this configuration.

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Furquan Shaikh furquan@google.com Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 19:47:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim wonkyu.kim@intel.com Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Furquan Shaikh (Code Review)

8:47 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 10: Code-Review+2

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 19:47:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Wonkyu Kim (Code Review)

10 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri

...

partner bug - I think it can be done as part of the same bug for TCSS enabling. […]

Done

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-Comment-Date: Fri, 31 Jan 2020 21:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim wonkyu.kim@intel.com Comment-In-Reply-To: Furquan Shaikh furquan@google.com Gerrit-MessageType: comment

Patrick Georgi (Code Review)

1 Feb 1 Feb

8:55 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

soc/intel/tigerlake: Configure TCSS xHCI and xDCI

Configure xHCI, xDCI according to board design

BUG=none BRANCH=none TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 10 insertions(+), 2 deletions(-)

Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3f980d1..4f57b0e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -218,6 +218,10 @@ FORCE_ENABLE, } CnviBtAudioOffload;

+ /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 9c105ca..fc3155f 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -105,6 +105,10 @@ /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));

-- To view, visit https://review.coreboot.org/c/coreboot/+/38624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Gerrit-Change-Number: 38624 Gerrit-PatchSet: 11 Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: Furquan Shaikh furquan@google.com Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Aaron Durbin adurbin@chromium.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com Gerrit-MessageType: merged

9elements QA (Code Review)

9:06 p.m.

New subject: Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS xHCI and xDCI

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )

Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................

Patch Set 11:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/386 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/385 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/384

Please note: This test is under development and might not be accurate at all!

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participants (7)

9elements QA (Code Review)
build bot (Jenkins) (Code Review)
Furquan Shaikh (Code Review)
Patrick Georgi (Code Review)
Paul Menzel (Code Review)
Pratikkumar V Prajapati (Code Review)
Wonkyu Kim (Code Review)