2 comments:
File src/soc/intel/tigerlake/chip.h:
Patch Set #3, Line 233: TcssAuxOri
Why do these have to be done by FSP? These are documented EDS registers which can be set by coreboot.
File src/soc/intel/tigerlake/fsp_params_tgl.c:
memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg,
sizeof(config->IomTypeCPortPadCfg));
Have you tried doing:
memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
to see if it boots fine without the assert? and ensure that the required pads are configured before calling into FSP-S?
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