Patrick Elsen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
[WIP]mainboard/lenovo: do initial commit for t540p
Based off of t440p.
Change-Id: I02ecde6999d1b5ca7741371273edd90297899fa0 Signed-off-by: Patrick Elsen pelsen@xfbs.net --- A src/mainboard/lenovo/t540p/Kconfig A src/mainboard/lenovo/t540p/Kconfig.name A src/mainboard/lenovo/t540p/Makefile.inc A src/mainboard/lenovo/t540p/acpi/ec.asl A src/mainboard/lenovo/t540p/acpi/platform.asl A src/mainboard/lenovo/t540p/acpi/superio.asl A src/mainboard/lenovo/t540p/acpi_tables.c A src/mainboard/lenovo/t540p/board_info.txt A src/mainboard/lenovo/t540p/devicetree.cb A src/mainboard/lenovo/t540p/dsdt.asl A src/mainboard/lenovo/t540p/gma-mainboard.ads A src/mainboard/lenovo/t540p/gpio.c A src/mainboard/lenovo/t540p/hda_verb.c A src/mainboard/lenovo/t540p/mainboard.c A src/mainboard/lenovo/t540p/romstage.c A src/mainboard/lenovo/t540p/smihandler.c 16 files changed, 819 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38204/1
diff --git a/src/mainboard/lenovo/t540p/Kconfig b/src/mainboard/lenovo/t540p/Kconfig new file mode 100644 index 0000000..9c136a4 --- /dev/null +++ b/src/mainboard/lenovo/t540p/Kconfig @@ -0,0 +1,41 @@ +if BOARD_LENOVO_THINKPAD_T540P + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select CPU_INTEL_HASWELL + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default lenovo/t540p + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T540p" + +config VGA_BIOS_FILE + string + default "pci8086,0416.rom" + +config VGA_BIOS_ID + string + default "8086,0416" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/t540p/Kconfig.name b/src/mainboard/lenovo/t540p/Kconfig.name new file mode 100644 index 0000000..a7c6910 --- /dev/null +++ b/src/mainboard/lenovo/t540p/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T540P + bool "ThinkPad T540p" diff --git a/src/mainboard/lenovo/t540p/Makefile.inc b/src/mainboard/lenovo/t540p/Makefile.inc new file mode 100644 index 0000000..fa6e7af --- /dev/null +++ b/src/mainboard/lenovo/t540p/Makefile.inc @@ -0,0 +1,3 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t540p/acpi/ec.asl b/src/mainboard/lenovo/t540p/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t540p/acpi/platform.asl b/src/mainboard/lenovo/t540p/acpi/platform.asl new file mode 100644 index 0000000..dfced7a --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/platform.asl @@ -0,0 +1,12 @@ +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, _TZ.MEB1) + Store (0, _TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + _SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t540p/acpi/superio.asl b/src/mainboard/lenovo/t540p/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t540p/acpi_tables.c b/src/mainboard/lenovo/t540p/acpi_tables.c new file mode 100644 index 0000000..5dc98d8 --- /dev/null +++ b/src/mainboard/lenovo/t540p/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/t540p/board_info.txt b/src/mainboard/lenovo/t540p/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/lenovo/t540p/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/lenovo/t540p/devicetree.cb b/src/mainboard/lenovo/t540p/devicetree.cb new file mode 100644 index 0000000..3ebaa42 --- /dev/null +++ b/src/mainboard/lenovo/t540p/devicetree.cb @@ -0,0 +1,166 @@ +chip northbridge/intel/haswell + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + register "gpu_cpu_backlight" = "0x12ba12ba" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x12ba12ba" + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x89" + register "pirqd_routing" = "0x87" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x86" + register "sata_ahci" = "1" + register "sata_port_map" = "0x21" + device pci 14.0 on # xHCI Controller + subsystemid 0x17aa 0x2210 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x2210 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x17aa 0x2210 + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:153a + subsystemid 0x17aa 0x2210 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x2210 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x2210 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x2210 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x2210 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x17aa 0x2210 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x2210 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x2210 + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa7" + register "config1" = "0x0d" + register "config2" = "0xa8" + register "config3" = "0xc4" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x81" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x9d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x2210 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x2210 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x2210 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x2210 + end + device pci 03.0 on # Mini-HD audio Audio controller + subsystemid 0x17aa 0x2210 + end + end +end diff --git a/src/mainboard/lenovo/t540p/dsdt.asl b/src/mainboard/lenovo/t540p/dsdt.asl new file mode 100644 index 0000000..4838877 --- /dev/null +++ b/src/mainboard/lenovo/t540p/dsdt.asl @@ -0,0 +1,31 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/lynxpoint/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/t540p/gma-mainboard.ads b/src/mainboard/lenovo/t540p/gma-mainboard.ads new file mode 100644 index 0000000..d7afe73 --- /dev/null +++ b/src/mainboard/lenovo/t540p/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t540p/gpio.c b/src/mainboard/lenovo/t540p/gpio.c new file mode 100644 index 0000000..a351508 --- /dev/null +++ b/src/mainboard/lenovo/t540p/gpio.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio3 = GPIO_LEVEL_LOW, + .gpio4 = GPIO_LEVEL_LOW, + .gpio5 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t540p/hda_verb.c b/src/mainboard/lenovo/t540p/hda_verb.c new file mode 100644 index 0000000..8574e4e --- /dev/null +++ b/src/mainboard/lenovo/t540p/hda_verb.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x80862807, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x0, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x0, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x0, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t540p/mainboard.c b/src/mainboard/lenovo/t540p/mainboard.c new file mode 100644 index 0000000..3440a0a --- /dev/null +++ b/src/mainboard/lenovo/t540p/mainboard.c @@ -0,0 +1,17 @@ +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +void h8_mainboard_init_dock(void) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t540p/romstage.c b/src/mainboard/lenovo/t540p/romstage.c new file mode 100644 index 0000000..4ecf202 --- /dev/null +++ b/src/mainboard/lenovo/t540p/romstage.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 0, /* mobile */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* note that SPD addresses are left-shifted by 1. */ + .spd_addresses = { 0xa0, 0, 0xa2, 0 }, + .ec_present = 1, + .gbe_enable = 1, + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, + { 1, 1 }, + { 1, 1 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = rcba_config, + }; + + romstage_common(&romstage_params); +} diff --git a/src/mainboard/lenovo/t540p/smihandler.c b/src/mainboard/lenovo/t540p/smihandler.c new file mode 100644 index 0000000..9f5044a --- /dev/null +++ b/src/mainboard/lenovo/t540p/smihandler.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +/* lynxpoint doesn't have gpi_route_interrupt, so add it */ +#define GPI_DISABLE 0x00 +#define GPI_IS_SMI 0x01 +#define GPI_IS_SCI 0x02 +#define GPI_IS_NMI 0x03 + +static void gpi_route_interrupt(u8 gpi, u8 mode) +{ + u32 gpi_rout; + + gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + gpi_rout &= ~(3 << (2 * gpi)); + gpi_rout |= ((mode & 3) << (2 * gpi)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, + * enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38204/1/src/mainboard/lenovo/t540p/... File src/mainboard/lenovo/t540p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38204/1/src/mainboard/lenovo/t540p/... PS1, Line 8: install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); line over 96 characters
Hello Alexander Couzens, Patrick Rudolph, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38204
to look at the new patch set (#2).
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
[WIP]mainboard/lenovo: do initial commit for t540p
Based off of t440p.
Change-Id: I02ecde6999d1b5ca7741371273edd90297899fa0 Signed-off-by: Patrick Elsen pelsen@xfbs.net --- A src/mainboard/lenovo/t540p/Kconfig A src/mainboard/lenovo/t540p/Kconfig.name A src/mainboard/lenovo/t540p/Makefile.inc A src/mainboard/lenovo/t540p/acpi/ec.asl A src/mainboard/lenovo/t540p/acpi/platform.asl A src/mainboard/lenovo/t540p/acpi/superio.asl A src/mainboard/lenovo/t540p/acpi_tables.c A src/mainboard/lenovo/t540p/board_info.txt A src/mainboard/lenovo/t540p/devicetree.cb A src/mainboard/lenovo/t540p/dsdt.asl A src/mainboard/lenovo/t540p/gma-mainboard.ads A src/mainboard/lenovo/t540p/gpio.c A src/mainboard/lenovo/t540p/hda_verb.c A src/mainboard/lenovo/t540p/mainboard.c A src/mainboard/lenovo/t540p/romstage.c A src/mainboard/lenovo/t540p/smihandler.c 16 files changed, 891 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38204/2
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 2:
'upstream' PR: https://github.com/coreboot/coreboot/pull/17
Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 2:
I've added few more patches to align with the rest of the boards.
https://github.com/Jikstra/coreboot/pull/1
Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38204/2/src/mainboard/lenovo/t540p/... File src/mainboard/lenovo/t540p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38204/2/src/mainboard/lenovo/t540p/... PS2, Line 2: register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" : register "gfx.ndid" = "3" Do we need these gfx.[n]did in devicetrees? I've tried to grep through ./src directory and cannot find anything related.
Jonas M has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38204/2/src/mainboard/lenovo/t540p/... File src/mainboard/lenovo/t540p/hda_verb.c:
https://review.coreboot.org/c/coreboot/+/38204/2/src/mainboard/lenovo/t540p/... PS2, Line 21: 0x80862807, /* Codec Vendor / Device ID: Intel */ : 0x80860101, /* Subsystem ID */ The T540P has two codecs. 0x80862807 is the Haswell HDMI codec
Jonas M has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38204/1/src/mainboard/lenovo/t540p/... File src/mainboard/lenovo/t540p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38204/1/src/mainboard/lenovo/t540p/... PS1, Line 8: GMA_INT15_ACTIVE_LFP_INT_LVDS Is this needed? This device uses eDP, not LVDS.
Peter Lemenkov has uploaded a new patch set (#3) to the change originally created by Patrick Elsen. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
[WIP]mainboard/lenovo: do initial commit for t540p
Based off of t440p.
Change-Id: I02ecde6999d1b5ca7741371273edd90297899fa0 Signed-off-by: Patrick Elsen pelsen@xfbs.net --- A src/mainboard/lenovo/t540p/Kconfig A src/mainboard/lenovo/t540p/Kconfig.name A src/mainboard/lenovo/t540p/Makefile.inc A src/mainboard/lenovo/t540p/acpi/ec.asl A src/mainboard/lenovo/t540p/acpi/platform.asl A src/mainboard/lenovo/t540p/acpi/superio.asl A src/mainboard/lenovo/t540p/acpi_tables.c A src/mainboard/lenovo/t540p/board_info.txt A src/mainboard/lenovo/t540p/devicetree.cb A src/mainboard/lenovo/t540p/dsdt.asl A src/mainboard/lenovo/t540p/gma-mainboard.ads A src/mainboard/lenovo/t540p/gpio.c A src/mainboard/lenovo/t540p/hda_verb.c A src/mainboard/lenovo/t540p/mainboard.c A src/mainboard/lenovo/t540p/romstage.c A src/mainboard/lenovo/t540p/smihandler.c 16 files changed, 823 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/38204/3
Jonas M has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 3: Code-Review-1
(1 comment)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38204/3/src/mainboard/lenovo/t540p/... File src/mainboard/lenovo/t540p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/38204/3/src/mainboard/lenovo/t540p/... PS3, Line 22: GMA_INT15_ACTIVE_LFP_INT_LVDS Shouldn't this be GMA_INT15_ACTIVE_LFP_EDP?
Brian Blevins has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38204 )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Patch Set 3:
Any progress on this? Anyone flashed this patch on their systems? If so, is everything working? I have a T540p so this would be quite pleasant if it did work.
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/38204?usp=email )
Change subject: [WIP]mainboard/lenovo: do initial commit for t540p ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Brian Blevins (Code Review) -
build bot (Jenkins) (Code Review)
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Idwer Vollering (Code Review)
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Jonas M (Code Review)
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Martin L Roth (Code Review)
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Patrick Elsen (Code Review)
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Peter Lemenkov (Code Review)