Change in coreboot[master]: soc/intel/tigerlake: add soc implementation for ETR address API
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/tigerlake/pmutil.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37555/1
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f8609..c163dc2 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -177,6 +177,12 @@ return (uintptr_t)pmc_mmio_regs(); }
+ +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config;
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 3: Code-Review+1
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 3: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG@9 PS3, Line 9: Add soc implementation for the new ETR address API. Not needed, as it’s the same as the commit message summary.
Hello Ravishankar Sarawadi, Patrick Rudolph, Karthik Ramasubramanian, Subrata Banik, Michael Niewöhner, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37555
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/tigerlake/pmutil.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37555/4
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG@9 PS3, Line 9: Add soc implementation for the new ETR address API.
Not needed, as it’s the same as the commit message summary.
Updated commit message.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37555/3//COMMIT_MSG@9 PS3, Line 9: Add soc implementation for the new ETR address API.
Updated commit message.
Done
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 4: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
Patch Set 4: Code-Review+1
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37555 )
Change subject: soc/intel/tigerlake: add soc implementation for ETR address API ......................................................................
soc/intel/tigerlake: add soc implementation for ETR address API
Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver.
Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra aamir.bohra@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555 Reviewed-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.corp-partner.google.com Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/pmutil.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Ravishankar Sarawadi: Looks good to me, but someone else must approve Maulik V Vaghela: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 53f8609..c163dc2 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -177,6 +177,12 @@ return (uintptr_t)pmc_mmio_regs(); }
+ +uint32_t *soc_pmc_etr_addr(void) +{ + return (uint32_t *)(soc_read_pmc_base() + ETR); +} + void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_tigerlake_config *config;
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Aamir Bohra (Code Review) -
Karthik Ramasubramanian (Code Review)
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Maulik V Vaghela (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)
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Ravishankar Sarawadi (Code Review)
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Wonkyu Kim (Code Review)