Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33161
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
mb/google/hatch: Enable LTR for PCIe ports
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2
BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33161/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9d10cac..1123d53 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -72,6 +72,7 @@
# Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -79,6 +80,7 @@
# PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3"
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
Patch Set 1: Code-Review+1
Did you measure the power usage before and after.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+1
Did you measure the power usage before and after.
No, I don't have the setup to do the power measurement. But, the power team is working on it.
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
Patch Set 1: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
mb/google/hatch: Enable LTR for PCIe ports
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2
BUG=b:134195632 TEST=Verified L1 substate with lspci on hatch: Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161 Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Paul Fagerburg: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 9d10cac..1123d53 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -72,6 +72,7 @@
# Enable Root port 9(x4) for NVMe. register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" # RP 9 uses CLK SRC 1 register "PcieClkSrcUsage[1]" = "8" # ClkReq-to-ClkSrc mapping for CLK SRC 1 @@ -79,6 +80,7 @@
# PCIe port 14 for M.2 E-key WLAN register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" # RP 14 uses CLK SRC 3 register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3"
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Furquan Shaikh (Code Review) -
Patrick Georgi (Code Review)
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Paul Fagerburg (Code Review)
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Paul Menzel (Code Review)