3 Jun
2019
3 Jun
'19
1:32 p.m.
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33161 )
Change subject: mb/google/hatch: Enable LTR for PCIe ports ......................................................................
Patch Set 1: Code-Review+1
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab
Gerrit-Change-Number: 33161
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Paul Fagerburg pfagerburg@chromium.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: Philip Chen philipchen@google.com
Gerrit-Reviewer: Shelley Chen shchen@google.com
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Mon, 03 Jun 2019 13:32:28 +0000
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