[M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter - coreboot-gerrit

2 Mar 2023


      Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.
Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 )
Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter
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Patch Set 4:
(1 comment)
Patchset:
PS2:
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Why is `sustained_power_limit_mW` staying when using it is an error? […]
Hi Tim,
STT usually be enabled when system has full chassis, before that, we still need to configure sustained_power_limit_mW, and it's not allowed to update its value by DPTC when STT enabled.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a
Gerrit-Change-Number: 73124
Gerrit-PatchSet: 4
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