Attention is currently required from: Arthur Heymans.
Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73087 )
Change subject: mb/intel/dq67sw: Add a new mainboard ......................................................................
Patch Set 3:
(4 comments)
Patchset:
PS3: Thanks for having a look!
File src/mainboard/intel/dq67sw/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/73087/comment/9cc4eef2_3e2955a2 PS2, Line 4: chip cpu/intel/model_206ax : device cpu_cluster 0 on end : # FIXME: check all registers : register "acpi_c1" = "1" : register "acpi_c2" = "3" : register "acpi_c3" = "5" : end
remove. This is now in the chipset.cb.
Done
https://review.coreboot.org/c/coreboot/+/73087/comment/803b1aef_28b3bcea PS2, Line 14: register "gen2_dec" = "0x000c02a1"
Which HW uses this?
The line is from autoport and this is how the vendor fw sets up this register. I'm not sure if I understand the chipset documentation correctly - does it enable decoding of the I/O port range 0x2a0-0x2af, with the mask 0xc making it ignore those address bits where it differs from GEN1_DEC?
base: 0x0290 = 0b0000001010010000 base: 0x02a0 = 0b0000001010100000 mask: 0xc<<2 = 0b 00110000 16 bytes: 0b000000000000xxxx
To me this looks like it wants to make the same device available on both ranges..
Only 0x290-0x29f shows up in /proc/ioports (old log, older linux, with vendor fw):
0290-029f : pnp 00:01 0295-0296 : w83627ehf 0295-0296 : w83627ehf
With corebooot this shows up after loading the nct6775 driver (linux-5.19.17):
0295-0296 : nct6775 0295-0296 : nct6775
And finally I tried reading some addresses with Aaron Durbin's iotools:
$ sudo ./iotools io_read32 0x2a0 0xffffffff (same for 0x2a4, 0x2a8. 0x2ac)
I removed the line now and I don't see any obvious changes.. so should we leave it out?
https://review.coreboot.org/c/coreboot/+/73087/comment/cfe6adf7_20a0a70f PS2, Line 20: device pci 16.0 on # Management Engine Interface 1 : subsystemid 0x8086 0x2008 : end : device pci 16.1 off # Management Engine Interface 2 : end : device pci 16.2 on # Management Engine IDE-R : subsystemid 0x8086 0x2008 : end : device pci 16.3 on # Management Engine KT : subsystemid 0x8086 0x2008 : end : device pci 19.0 on # Intel Gigabit Ethernet : subsystemid 0x8086 0x2008 : end : device pci 1a.0 on # USB2 EHCI #2 : subsystemid 0x8086 0x2008 : end : device pci 1b.0 on # High Definition Audio : subsystemid 0x8086 0x2008 : end : device pci 1c.0 on # PCIe Port #1 : subsystemid 0x8086 0x2008 : end : device pci 1c.1 off # PCIe Port #2 : end : device pci 1c.2 off # PCIe Port #3 : end : device pci 1c.3 off # PCIe Port #4 : end : device pci 1c.4 on # PCIe Port #5 : subsystemid 0x8086 0x2008 : end : device pci 1c.5 off # PCIe Port #6 : end : device pci 1c.6 on # PCIe Port #7 : subsystemid 0x8086 0x2008 : end : device pci 1c.7 off # PCIe Port #8 : end : device pci 1d.0 on # USB2 EHCI #1 : subsystemid 0x8086 0x2008 : end : device pci 1e.0 on # PCI bridge : subsystemid 0x8086 0x2008 : end : device pci 1f.0 on # LPC bridge
Please use the alias defined in northbridge/intel/sandybridge/chipset. […]
Like this? I also moved the host_bridge, peg10 and igd entries to the top, which is where northbridge/intel/sandybridge/chipset.cb has them.
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Michael Büchler (Code Review)