Change in coreboot[master]: soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37659 )
Change subject: soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h ......................................................................
soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h
gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members.
Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 4 files changed, 0 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/37659/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f08fd0a..85c33db 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -45,12 +45,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index ec625a0..0687513 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -35,12 +35,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 63626663..b189a16 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -73,11 +73,6 @@ uint8_t pirqg_routing; uint8_t pirqh_routing;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 32dc02c..5e0fcd1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -35,12 +35,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37659 )
Change subject: soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37659 )
Change subject: soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37659 )
Change subject: soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h ......................................................................
soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h
gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members.
Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/skylake/chip.h M src/soc/intel/tigerlake/chip.h 4 files changed, 0 insertions(+), 23 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f08fd0a..85c33db 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -45,12 +45,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index ec625a0..0687513 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -35,12 +35,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 63626663..b189a16 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -73,11 +73,6 @@ uint8_t pirqg_routing; uint8_t pirqh_routing;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 32dc02c..5e0fcd1 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -35,12 +35,6 @@ /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config;
- /* GPE configuration */ - uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ - uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ - uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ - uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ - /* Gpio group routed to each dword of the GPE0 block. Values are * of the form GPP_[A:G] or GPD. */ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
-
Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
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HAOUAS Elyes (Code Review)
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Patrick Georgi (Code Review)