Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 46 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index a28fac6..bbeee1f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -79,6 +79,7 @@ #define VMD_FUNC_NUM 0x05
#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 32c316d..6523b6d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -128,6 +128,7 @@ #define HPET0_FUNC_NUM 0x00
#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 332b9a4..c9ffeb6 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -11,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/util.h> #include <fsp/util.h> +#include <security/intel/txt/txt_platform.h> +#include <soc/pci_devs.h>
struct map_entry { uint32_t reg; @@ -88,6 +90,17 @@ } }
+static void configure_dpr(struct device *dev) +{ + const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + + dpr.size = dpr.top - cbmem_top_mb; + dpr.lock = 1; + dpr.epm = 1; + pci_write_config32(dev, VTD_LTDPR, dpr.raw); +} + /* * Host Memory Map: * @@ -127,6 +140,8 @@ * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) * +--------------------------+ * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | DPR | * +--------------------------+ cbmem_top * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) * +--------------------------+ @@ -199,6 +214,13 @@ LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); reserved_ram_resource(dev, index++, base_kb, size_kb);
+ /* Reserve and set up DPR */ + configure_dpr(dev); + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.size) + reserved_ram_resource(dev, index++, (dpr.top - dpr.size) << 10, dpr.size << 10); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); @@ -290,3 +312,25 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = mmapvtd_ids }; + +static void vtd_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + configure_dpr(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +}; + +/* VTD devices on other stacks */ +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMAP_VTD_STACK_CFG_REG_DEVID, +};
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 2: Code-Review+1
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... PS5, Line 320: configure_dpr(dev); why not in init?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... PS5, Line 320: configure_dpr(dev);
why not in init?
This should probably happen after clearing the memory has happened (BS_DEV_INIT, BS_ON_EXIT). If it is done in .final it also happens before LockConfig.
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46818
to look at the new patch set (#6).
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/6
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46818
to look at the new patch set (#7).
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/7
Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46818
to look at the new patch set (#10).
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/10
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46818/5/src/soc/intel/xeon_sp/uncor... PS5, Line 320: configure_dpr(dev);
why not in init? […]
Looks like FSP-S locks down this register. So I'll keep it in read_resources.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46818/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46818/10//COMMIT_MSG@9 PS10, Line 9: TSEG_BASE and the cbmem_top Since TSEG base >= cbmem_top, I'd say:
... cbmem_top and TSEG base.
https://review.coreboot.org/c/coreboot/+/46818/10/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46818/10/src/soc/intel/xeon_sp/unco... PS10, Line 234: Spurious \n
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46818
to look at the new patch set (#12).
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between cbmem_top and TSEG base. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/12
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46818/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46818/10//COMMIT_MSG@9 PS10, Line 9: TSEG_BASE and the cbmem_top
Since TSEG base >= cbmem_top, I'd say: […]
Done
https://review.coreboot.org/c/coreboot/+/46818/10/src/soc/intel/xeon_sp/unco... File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/46818/10/src/soc/intel/xeon_sp/unco... PS10, Line 234:
Spurious \n
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 12: Code-Review+2
Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46818
to look at the new patch set (#13).
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between cbmem_top and TSEG base. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/13
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
Patch Set 13: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46818 )
Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ......................................................................
soc/intel/xeon_sp: Configure DPR on all stacks
Configure DPR to span the region between cbmem_top and TSEG base. This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 51 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 53503df..198d385 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -78,6 +78,7 @@ #define VMD_FUNC_NUM 0x05
#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 3539555..ce223cc 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -128,6 +128,7 @@ #define HPET0_FUNC_NUM 0x00
#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 15a9f0f..de29dea 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -11,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/util.h> #include <fsp/util.h> +#include <security/intel/txt/txt_platform.h> +#include <soc/pci_devs.h>
struct map_entry { uint32_t reg; @@ -88,6 +90,20 @@ } }
+static void configure_dpr(struct device *dev) +{ + const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + + /* The DPR lock bit has to be set sufficiently early. It looks like + * it cannot be set anymore after FSP-S. + */ + dpr.lock = 1; + dpr.epm = 1; + dpr.size = dpr.top - cbmem_top_mb; + pci_write_config32(dev, VTD_LTDPR, dpr.raw); +} + /* * Host Memory Map: * @@ -127,6 +143,8 @@ * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) * +--------------------------+ * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | DPR | * +--------------------------+ cbmem_top * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) * +--------------------------+ @@ -203,6 +221,16 @@ LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); reserved_ram_resource(dev, index++, base_kb, size_kb);
+ /* Reserve and set up DPR */ + configure_dpr(dev); + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.size) { + uint32_t dpr_base_k = (dpr.top - dpr.size) << 10; + uint32_t dpr_size_k = dpr.size << 10; + reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); + LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k); + } + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); @@ -294,3 +322,24 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = mmapvtd_ids }; + +static void vtd_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + configure_dpr(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &soc_pci_ops, +}; + +/* VTD devices on other stacks */ +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMAP_VTD_STACK_CFG_REG_DEVID, +};
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Hung-Te Lin (Code Review)
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Patrick Rudolph (Code Review)