Change in coreboot[master]: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM.

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/1

diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 2a54e24..6665eb0 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -27,6 +27,7 @@
    select CACHE_MRC_SETTINGS
    select PARALLEL_MP
    select C_ENVIRONMENT_BOOTBLOCK
+	select ROMSTAGE_CACHED_CBMEM

config CBFS_SIZE
    hex
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 8013af9..e8729fb 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -33,6 +33,7 @@
 #include <mrc_cache.h>
 #include <timestamp.h>
 #include <types.h>
+#include <cpu/x86/mtrr.h>

#include "iomap.h"
 #include "x4x.h"
@@ -718,6 +719,7 @@
    pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1);
    printk(BIOS_DEBUG, "RAM initialization finished.\n");

+	setup_romstage_wb_cbmem_cache();
    cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);
    if (!fast_boot)
    	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION,

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, Damien Zammit,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#2).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM.

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/2

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#5).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/5

[Arthur Heymans (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#7).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/7

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

Patch Set 7:

This on the ancestors

git fetch "https://review.coreboot.org/coreboot" refs/changes/13/37213/7 && git checkout FETCH_HEAD

correctly boot on the ASRock E350M1 (AMD Fusion, AGESA Family 14h)) and seem to save 9 ms according to the timestamps (but only did two boots comparing it to the results in the board status repository).

```
$ sudo cbmem -t
33 entries total:

0:1st timestamp                                     7,886
  11:start of bootblock                                13,453 (5,567)
  12:end of bootblock                                  14,770 (1,317)
  13:starting to load romstage                         15,380 (609)
  14:finished loading romstage                         15,462 (81)
   1:start of romstage                                 15,770 (308)
   2:before ram initialization                         127,956 (112,185)
   3:after ram initialization                          402,574 (274,617)
  17:starting LZ4 decompress (ignore for x86)          414,089 (11,515)
  18:finished LZ4 decompress (ignore for x86)          415,027 (937)
 100:start of postcar                                  416,485 (1,458)
 101:end of postcar                                    416,486 (0)
   8:starting to load ramstage                         416,596 (110)
  15:starting LZMA decompress (ignore for x86)         416,632 (36)
  16:finished LZMA decompress (ignore for x86)         507,218 (90,585)
   9:finished loading ramstage                         507,264 (46)
  10:start of ramstage                                 507,286 (21)
  30:device enumeration                                511,203 (3,917)
  40:device configuration                              649,123 (137,920)
  50:device enable                                     662,052 (12,928)
  60:device initialization                             662,521 (468)
  65:Option ROM initialization                         676,528 (14,007)
  66:Option ROM copy done                              708,377 (31,849)
  67:Option ROM run done                               750,088 (41,710)
  70:device setup done                                 750,532 (443)
  75:cbmem post                                        1,000,542 (250,010)
  80:write tables                                      1,000,543 (1)
  85:finalize chips                                    1,007,883 (7,340)
  90:load payload                                      1,007,888 (4)
  15:starting LZMA decompress (ignore for x86)         1,008,407 (519)
  16:finished LZMA decompress (ignore for x86)         1,034,267 (25,860)
  15:starting LZMA decompress (ignore for x86)         1,034,338 (70)
  16:finished LZMA decompress (ignore for x86)         1,116,042 (81,703)
  99:selfboot jump                                     1,116,134 (92)

Total Time: 1,108,233
```

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#8).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/socket_LGA775/Kconfig
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
3 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/8

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#13).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/socket_LGA775/Kconfig
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
3 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/13

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#14).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/socket_LGA775/Kconfig
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
3 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/14

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37213

to look at the new patch set (#15).

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

[TESTONLY]nb/intel/x4x: Cache cbmem in romstage

Probably not a good idea to avoid eviction in romstage.

TESTED: works fine on P5QL-EM: ~2.5ms faster!

Change-Id: Ib8622f4501f6df005baad003f41f4be3d239f2c6
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/socket_LGA775/Kconfig
M src/northbridge/intel/x4x/Kconfig
M src/northbridge/intel/x4x/raminit.c
3 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37213/15

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

Patch Set 15:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37213/comment/0c56cd37_0dbc5793 
PS15, Line 11: TESTED: works fine on P5QL-EM: ~2.5ms faster!
With which CPU?

[Arthur Heymans (Code Review)]

Attention is currently required from: Angel Pons.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

Patch Set 15:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/37213/comment/5f1736c6_bb1c55b9 
PS15, Line 11: TESTED: works fine on P5QL-EM: ~2.5ms faster!
> With which CPU?

Some Conroe cpu iirc. It's been more than 2 years so I don't remember. I don't intend to merge this as these CPUs don't have nonevict.

[Arthur Heymans (Code Review)]

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37213 )

Change subject: [TESTONLY]nb/intel/x4x: Cache cbmem in romstage
......................................................................

Abandoned